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PDF 8SLVD1212 Data sheet ( Hoja de datos )
| Número de pieza | 8SLVD1212 | |
| Descripción | LVDS Output Fanout Buffer | |
| Fabricantes | IDT | |
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1:12, LVDS Output Fanout Buffer
8SLVD1212
Datasheet
General Description
The 8SLVD1212 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1212 is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1212 ideal for those clock distribution applications demanding
well-defined performance and repeatability. Two selectable
differential inputs and twelve low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pins
• Output skew: 45ps (max)
• Propagation delay: 310ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz - 20MHz: 77fs (typical)
• Maximum device current consumption (IDD): 213mA
• 2.5V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Pin Assignment
SEL
PCLK1
nPCLK1
VREF1
VDD
VDD
VREF0
nPCLK0
PCLK0
nc
40 39 38 37 36 35 34 33 32 31
1
2
3
4
5 8SLVD1212
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
GND
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
GND
40-Lead VFQFN
6.0mm x 6.0mm x 0.9mm package body
©2016 Integrated Device Technology, Inc.
1
Revision 3, July 5, 2016
1 page  
8SLVD1212 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
Input Sink/Source, IREF
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
ESD - Human Body Model1
ESD - Charged Device Mode1
NOTE 1: According to JEDEC/JS-001-2012/ 22-C101E.
Rating
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VDD Power Supply Voltage
IDD Power Supply Current
Q0 to Q11 terminated 100
between nQx, Qx
2.375
Typical
2.5V
184
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VMID
VIH
VIL
IIH
IIL
Input voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
Floating
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
0.7 * VDD
-0.3
-150
Typical
VDD / 2
Maximum
2.625
213
Units
V
mA
Maximum
VDD + 0.3
0.2 * VDD
150
Units
V
V
V
µA
µA
©2016 Integrated Device Technology, Inc.
5
Revision 3, July 5, 2016
5 Page 
8SLVD1212 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V1 in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 2.5V,
R1 and R2 value should be adjusted to set V1 at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Suggested edge
rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2016 Integrated Device Technology, Inc.
11
Revision 3, July 5, 2016
11 Page | ||
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| PDF Descargar | [ Datasheet 8SLVD1212.PDF ] | |
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