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PDF W255 Data sheet ( Hoja de datos )
| Número de pieza | W255 | |
| Descripción | 200-MHz 24-Output Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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W255
200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
Features
Functional Description
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
BUF_IN
SDATA
SCLOCK
SMBus
Decoding
PWR_DWN#
SEL_DDR
Power Down Control
Pin Configuration[1]
FBOUT
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
FBOUT
VDD3.3_2.5
GND
DDR2T_SDRAM2 DDR0T_SDRAM10
DDR2C_SDRAM3 DDR0C_SDRAM11
DDR3T_SDRAM4 DRR1T_SDRAM0
DDR3C_SDRAM5 DDR1C_SDRAM1
DDR4T_SDRAM6
VDD3.3_2.5
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
DDR6T
BUF_IN
DDR6C
GND
DDR7T
DDR7C
DDR8T
DDR8C
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR9T
DDR4C_SDRAM7
DDR9C
DDR10T
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
DDR10C
SDATA
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
DDR11T
DDR11C
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07255 Rev. *D
Revised April 28, 2005
1 page  
Switching Characteristics (continued)[4]
Parameter
Name
Test Conditions
t4d
DDR Falling Edge Rate[3]
Measured between 20% to 80% of
output (refer to Figure 1)
t5 Output to Output Skew for DDR[3] All outputs equally loaded
t6
Output to Output Skew for
SDRAM[3]
All outputs equally loaded
t7 SDRAM Buffer LH Prop. Delay[3] Input edge greater than 1 V/ns
t8 SDRAM Buffer HL Prop. Delay[3] Input edge greater than 1 V/ns
Switching Waveforms
Duty Cycle Timing
t1
t2
W255
Min. Typ. Max. Unit
0.5 1.50 V/ns
100 ps
150 ps
5 10 ns
5 10 ns
All Outputs Rise/Fall Time
2.4V
OUTPUT 0.4V
t3
Output-Output Skew
2.4V
0.4V
t4
OUTPUT
OUTPUT
t5
SDRAM Buffer HH and LL Propagation Delay
INPUT
1.5V
OUTPUT
t6
1.5V
t7
3.3V
0V
Document #: 38-07255 Rev. *D
Page 5 of 10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet W255.PDF ] | |
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