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CD22101E Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD22101E
Beschreibung CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 13 Seiten
CD22101E Datasheet, Funktion
Semiconductor
CD22101, CD22102
[ /Title
(CD22
101,
CD221
02)
/Sub-
ject
(CMO
S4x4
x2
Cross-
point
Switch
with
Con-
trol
Mem-
ory)
/
Author
()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Tele-
com,
SLICs,
SLACs
, Tele-
phone,
Tele-
phony,
WLL,
Wire-
less
February 1999
Features
CNalOl CoRerEneCtOmrOaBalMSiAlMO:pLEcpENeliTncDEtaEatpDiPopRnR@OsEDh1PaU-L8rCAr0iTC0s-.Ec4Mo42mE-N77T47
CMOS 4
Description
x
4
x 2 Crosspoint Switch
with Control Memory
• Low ON Resistance . . . . . . . . . . . . 75(Typ) at VDD = 12V
• “Built - In” Latched Inputs
• Large Analog Signal Capability . . . . . . . . . . . . . . . ±VDD/2
• Switch Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 10MHz
• Matched Switch Characteristics
RON = 8(Typ) at VDD = 12V
• High Linearity - 0.25% Distortion (Typ) at f = 1kHz,
VIN = 5VP-P, VDD - VSS = 10V, and RL = 1k
• Standard CMOS Noise Immunity
Applications
• Telephone Systems
• PBX
• Studio Audio Switching
• Multisystem Bus Interconnect
Ordering Information
PART
NUMBER
CD22101E
TEMP.
RANGE (oC)
PACKAGE
-40 to 85 24 Ld PDIP
PKG. NO.
E24.6
CD22101 and CD22102 crosspoint switches consist of
4 x 4 x 2 arrays of crosspoints (transmission gates) with a
4-line to 16-line decoder and 16 latch circuits. Any one of
the sixteen crosspoint pairs can be selected by applying
the appropriate four-line address, corresponding
crosspoints in each array are turned on and off
simultaneously. Any number of crosspoints can be turned
on simultaneously.
In the CD22101, the selected crosspoint pair can be
turned on or off by applying a logic ONE or ZERO,
respectively, to the data input, and applying a ONE to the
strobe input. When the device is “powered up”, the states
of the 16 switches are indeterminate. Therefore, all
switches must be turned off by putting the strobe high,
data-in low, and then addressing all switches in
succession.
The selected pair of crosspoints in the CD22102 is turned
on by applying a logic ONE to the KA (set) input while a
logic ZERO is on the KB input, and turned off by applying
a logic ONE to the KB (reset) input while a logic ZERO is
on the KA input. In this respect, the control latches of the
CD22102 are similar to SET/RESET flip-flops. They differ,
however, in that the simultaneous application of ONEs to
the KA and KB inputs turns off (resets) all crosspoints. All
crosspoints in both devices must be turned off as VDD is
applied.
CD22101F
-55 to 125 24 Ld CERDIP F24.6
CD22102E
-40 to 85 24 Ld PDIP
E24.6
Pinouts
CD22101
(PDIP, SBDIP)
TOP VIEW
B1
C2
X2' 3
Y1' 4
Y2' 5
X4' 6
X3' 7
Y4' 8
Y3' 9
X1' 10
D 11
VSS 12
24 VDD
23 A
22 X2
21 Y1
20 Y2
19 X4
18 X3
17 Y4
16 Y3
15 X1
14 DATA
13 STROBE
CD22102
(PDIP)
TOP VIEW
B1
C2
X2' 3
Y1' 4
Y2' 5
X4' 6
X3' 7
Y4' 8
Y3' 9
X1' 10
D 11
VSS 12
24 VDD
23 A
22 X2
21 Y1
20 Y2
19 X4
18 X3
17 Y4
16 Y3
15 X1
14 KA
13 KB
Functional Diagram
CONTROL
DECODER
LATCH
16
16
16
IN (OUT)
4X4
SWITCH
OUT (IN)
4X4
SWITCH
OUT (IN)
IN (OUT)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
4-193
File Number 2871.3






CD22101E Datasheet, Funktion
CD22101, CD22102
Schematic Diagram
(NOTE) STROBE
13
(NOTE) DATA IN
14
24
VDD
23
A
(NOTE)
1
B
(NOTE)
2
C
(NOTE)
11
D
(NOTE)
12
VSS
TO X1’ Y1’
A
B
C
AD
DQ
ø
ø
LATCH
0
1
2
3
A
TO 15 OTHER
TO 15 OTHER
NANDS
LATCHS
B
KA (SET)
B (NOTE)
14
C
KB (RESET)
(NOTE)
13
A
B
C
D
CD22101
DQ
ø
ø
R
4
5
6
7
8
9
10
11
C
TO 15 OTHER
NANDS
12
13
14
15
D
D
TO 15 OTHER
LATCHES
CD22102
21
Y1 (Y41’)
TG TG TG TG
20
Y2
(Y52’)
TG TG TG TG
16
Y3 (Y93’)
TG TG TG TG
17 (Y84’)
Y4
TG TG TG TG
15
X1
(
10
X1’
)
22
X2
(
3
X2’
)
18
X3
(
7
X3’
)
19
X4
(
6
X4’
)
DETAIL OF TRANSMISSION GATES
VDD
IN VDD
DETAIL OF LATCHES
VDD ø
NOTE: INPUTS PROTECTED
BY COS/MOS
PROTECTION
NETWORK
D
VSS
p
n
ø
ø
p
n
Qø
Q
VSS
OUT
DECODER TRUTH TABLE
ADDRESS
ADDRESS
ABCD
SELECT
ABCD
SELECT
0 0 0 0 X1Y1 and X1’Y1’ 0 0 0 1 X1Y3 and X1’Y3’
1 0 0 0 X2Y1 and X2’Y1’ 1 0 0 1 X2Y3 and X2’Y3’
0 1 0 0 X3Y1 and X3’Y1’ 0 1 0 1 X3Y3 and X3’Y3’
1 1 0 0 X4Y1 and X4’Y1’ 1 1 0 1 X4Y3 and X4’Y3’
0 0 1 0 X1Y2 and X1’Y2’ 0 0 1 1 X1Y4 and X1’Y4’
1 0 1 0 X2Y2 and X2’Y2’ 1 0 1 1 X2Y4 and X2’Y4’
0 1 1 0 X3Y2 and X3’Y2’ 0 1 1 1 X3Y4 and X3’Y4’
1 1 1 0 X4Y2 and X4’Y2’ 1 1 1 1 X4Y4 and X4’Y4’
4-198

6 Page









CD22101E pdf, datenblatt
CD22101, CD22102
Test Circuits and Waveforms (Continued)
VIS
600
ANY
OFF
SWITCH
VOS
600
ISOLATION (dB) = 20 LOG -V-V--O-I--S-S-
-140
-120
-100
-80
-60
-40
TA = 25oC
RS = 600
RL = 600
7.5V, -7.5V, 3VRMS
5V, -5V, 2VRMS
VDD = 2.5V, VSS = -2.5V
VIS = 1VRMS
-20
102
103 104 105 106
INPUT SIGNAL FREQUENCY (Hz)
107
FIGURE 13. TEST CIRCUIT AND TYPICAL FEEDTHROUGH AS A FUNCTION OF FREQUENCY (ANY OFF SWITCH)
Typical Performance Curves
VDD = 2.5V, VSS = -2.5V
350
300
250
200
150
100 TA = 125oC
50 25oC
-55oC
0
-2 -1 0
1
INPUT SIGNAL (V)
2
FIGURE 14. TYPICAL ON RESISTANCE AS A FUNCTION OF
INPUT SIGNAL VOLTAGE AT VDD = -VSS = 2.5V
VDD = 5V, VSS = -5V
175
150
125
100
TA = 125oC
75
25oC
50
-55oC
25
0
-4
-2 0 2
INPUT SIGNAL (V)
4
FIGURE 15. TYPICAL ON RESISTANCE AS A FUNCTION OF
INPUT SIGNAL VOLTAGE AT VDD = -VSS = 5V
4-204

12 Page





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