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CAT5401 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer CAT5401
Beschreibung Quad Digital Potentiometer
Hersteller ON Semiconductor
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Gesamt 15 Seiten
CAT5401 Datasheet, Funktion
CAT5401
Quad Digital
Potentiometer (POT)
with 64 Taps
and SPI Interface
Description
The CAT5401 is four digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register.
The CAT5401 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Four Linear Taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface:
Mode (0, 0) and (1, 1)
Low Wiper Resistance, Typically 100 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current Less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
TSSOP24
Y SUFFIX
CASE 948AR
SOIC24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
CAT5401
SOIC24 (W)
(Top View)
NC
RL3
RH3
RW3
A0
SO
HOLD
SCK
RL2
RH2
RW2
NC
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCK
HOLD
1
CAT5401
TSSOP24 (Y)
(Top View)
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 Rev. 11
1
Publication Order Number:
CAT5401/D






CAT5401 Datasheet, Funktion
CAT5401
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min Typ
tSU
tH
tWH
tWL
fSCK
tLZ
tRI (Note 8)
tFI (Note 8)
tHD
tCD
tV
tHO
tDIS
tHZ
tCS
tCSS
tCSH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CL = 50 pF
50
50
125
125
DC
100
100
0
250
250
250
Table 8. POWER UP TIMING (Notes 8, 9)
Symbol
Parameter
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
Table 9. WRITE CYCLE LIMITS
Symbol
Parameter
Max
tWR Write Cycle Time
5
Table 10. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
NEND (Note 10)
TDR (Note 10)
VZAP (Note 10)
ILTH (Note 10)
Endurance
Data Retention
ESD Susceptibility
Latch-up
MILSTD883, Test Method 1033
MILSTD883, Test Method 1008
MILSTD883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Max Units
ns
ns
ns
ns
3 MHz
50 ns
2 ms
2 ms
ns
ns
250 ns
ns
250 ns
100 ns
ns
ns
ns
Max Units
1 ms
1 ms
Units
ms
Units
Cycles/Byte
Years
V
mA
http://onsemi.com
6

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CAT5401 pdf, datenblatt
CAT5401
Table 20. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
CS DEVICE ADDRESSES
INSTRUCTION
CS
0 1 0 1 0 0 A1 A0 1 1 1 0 R1 R0 P1 P0
High
Voltage
Write
Cycle
Table 21. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
CS DEVICE ADDRESSES
INSTRUCTION
CS
0 1 0 1 0 0 A1 A0 1 1 0 1 R1 R0 P1 P0
Table 22. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)
CS DEVICE ADDRESSES
INSTRUCTION
0 1 0 1 0 0 A1 A0 0 0 1 0 0 0 P1 P0 I/D I/D
DATA
...
CS
I/D I/D
NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
http://onsemi.com
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