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PDF CAT5241 Data sheet ( Hoja de datos )
| Número de pieza | CAT5241 | |
| Descripción | Quad Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
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CAT5241
Quad Digital
Potentiometer (POT)
with 64 Taps
and I2C Interface
Description
The CAT5241 is four Digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a I2C serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register (WCR).
The CAT5241 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Four Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via I2C Interface
Low Wiper Resistance, Typically 80 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
20-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
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TSSOP−20
Y SUFFIX
CASE 948AQ
SOIC−20
W SUFFIX
CASE 751BJ
PIN CONNECTIONS
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
1
CAT5241
SOIC−20 (W)
TSSOP−20 (Y)
(Top View)
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 20
1
Publication Order Number:
CAT5241/D
1 page  
CAT5241
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min Typ Max
ICC Power Supply Current
ISB Standby Current (VCC = 5.0 V)
fSCL = 400 kHz
VIN = GND or VCC;
SDA = GND;
RWX = GND (Note 8)
1
1
ILI Input Leakage Current
VIN = GND to VCC
ILO Output Leakage Current
VOUT = GND to VCC
VIL Input Low Voltage
VIH Input High Voltage
VOL1
Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
8. All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground.
−1
VCC x 0.7
10
10
VCC x 0.3
VCC + 1.0
0.4
Table 6. CAPACITANCE (Note 9) (TA = 25C, f = 1.0 MHz, VCC = +5.0 V)
Symbol
Parameter
Test Conditions
Min
Typ
Max
CI/O Input/Output Capacitance (SDA)
CIN Input Capacitance (A0, A1, A2, A3, SCL)
VI/O = 0 V
VIN = 0 V
8
6
Units
mA
mA
mA
mA
V
V
V
Units
pF
pF
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ
fSCL
TI (Note 9)
tAA
tBUF (Note 9)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 9)
tF (Note 9)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
Max Units
400 kHz
50 ns
0.9 ms
ms
ms
ms
ms
ms
ns
ns
0.3 ms
300 ns
ms
ns
Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
9. This parameter is tested initially and after a design or process change that affects the parameter.
Max Units
1 ms
1 ms
Table 9. WRITE CYCLE LIMITS (Note 10) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ Max Units
tWR Write Cycle Time
5 ms
10. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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5
5 Page 
CAT5241
The basic sequence of the three byte instructions is
illustrated in Figure 11. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by tWRL.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
maximum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 10. These instructions
transfer data between the host/processor and the CAT5241;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data Registers
to the associated Wiper Control Registers.
Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control Registers
to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6
and 12). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5241 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
T
A
R
Device ID
T
Internal
Address
A
C
K
I3 I2 I1
Instruction
Opcode
I0 P1 P0
Pot/WCR
Address
R1 R0
A
CK
Register
Address
Figure 10. Two-Byte Instruction Sequence
S
T
O
P
SDA
0 101
S
T
A
R
T
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Device ID
Internal
Address
ACK
I3
I2 I1 I0
Instruction
Opcode
P1 P0
Pot/WCR
Address
R1 R0
Data
Register
CAK
Address
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
AS
CT
KO
P
Figure 11. Three-Byte Instruction Sequence
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
T
A Device ID
R
Internal
Address
T
A
CK
I3 I2 I1 I0 P1 P0 R1 R0 CA
Instruction
Opcode
Pot/WCR
Address
Data K
Register
Address
I
N
C
1
I
N
C
2
Figure 12. Increment/Decrement Instruction Sequence
ID
N
C
E
C
n1
DS
E
C
n
T
O
P
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11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT5241.PDF ] | |
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