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PDF A6818 Data sheet ( Hoja de datos )
| Número de pieza | A6818 | |
| Descripción | DABiC-IV 32-Bit Serial Input Latched Source Driver | |
| Fabricantes | Allegro | |
| Logotipo |  |
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A6818
DABiC-IV 32-Bit Serial Input
Latched Source Driver
Features and Benefits
▪ Controlled output slew rate
▪ 60 V minimum output break down
▪ PNP active pull-downs
▪ Low-power CMOS logic and latches
▪ High-speed data storage
▪ High data-input rate
▪ Low output-saturation voltages
▪ Improved replacements for SN75518N, SN75518NF,
UCN5818x, and UCQ5818x
Package: 44 pin PLCC (suffix EP)
Description
The A6818 device combines a 32-bit CMOS shift register,
accompanying data latches and control circuitry, with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent displays, the 60 V and
–40 mA output ratings also allow this device to be used in
many other peripheral power driver applications. The A6818
features an increased data-input rate (compared with the older
UCN/UCQ5818x) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates are up to 33 MHz.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6810 (10-bit) and A6812 (20-bit).
The A6818 output source drivers are NPN Darlingtons,
capable of sourcing up to 40 mA. The controlled output slew
rate reduces electromagnetic noise, which is an important
consideration in systems that include telecommunications
and/or microprocessors and to meet government emissions
Not to scale
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
Continued on the next page…
Functional Block Diagram
V DD
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
LOGIC
SUPPLY
SERIAL
DATA OUT
MOS
BIPOLAR
VBB
LOAD
SUPPLY
GROUND
26182.128F
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
1 page  
A6818
DABiC-IV 32-Bit Serial Input
Latched Source Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E-
and A6818K-), VBB = 60 V, unless otherwise noted
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Characteristic
Symbol Test Conditions
Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current
Output Voltage
Output Pull-Down Current
Input Voltage
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Output Fall Time
Output Rise Time
ICEX
VOUT(1)
VOUT(0)
IOUT(0)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VIK
VOUT(1)
VOUT(0)
fc
IDD(1)
IDD(0)
IBB(1)
IBB(0)
tdis(BQ)
ten(BQ)
tp(STH-QL)
tp(STH-QH)
tf
tr
VOUT = 0 V
IOUT = -25 mA
IOUT = 1 mA
VOUT = 5 V to VBB
VIN = VDD
VIN = 0.8 V
IIN = -200 μA
IOUT = -200 μA
IOUT = 200 μA
All Outputs High
All Outputs Low
All Outputs High, No Load
All Outputs Low
CL = 30 pF, 50% to 50%
CL = 30 pF, 50% to 50%
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
— <-0.1 -15
57.5 58.3 —
— 1.0 1.5
2.5 5.0
—
2.2 —
—
— — 1.1
— <0.01 1.0
— <-0.01 -1.0
— -0.8 -1.5
2.8 3.05 —
— 0.15 0.3
10 33 —
— 0.25 0.75
— 0.25 0.75
— 4.5 9.0
— 0.2 20
— 0.7 2.0
— 1.8 3.0
— 0.7 2.0
— 1.8 3.0
2.4 — 12
2.4 — 12
— <-0.1 -15
57.5 58.3 —
— 1.0 1.5
2.5 5.0 —
3.3 — —
— — 1.7
— <0.01 1.0
— <-0.01 -1.0
— -0.8 -1.5
4.5 4.75 —
— 0.15 0.3
10 33 —
— 0.3 1.0
— 0.3 1.0
— 4.5 9.0
— 0.2 20
— 0.7 2.0
— 1.8 3.0
— 0.7 2.0
— 1.8 3.0
2.4 — 12
2.4 — 12
μA
V
V
mA
V
V
μA
μA
V
V
V
MHz
mA
mA
mA
μA
μs
μs
μs
μs
μs
μs
Output Slew Rate
dV/dt
RL = 2.3 k, CL 30 pF
4.0 — 20 4.0 — 20 V/μs
Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 μA
— 50 — — 50 —
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
ns
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet A6818.PDF ] | |
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