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DM9331A Schematic ( PDF Datasheet ) - DAVICOM

Teilenummer DM9331A
Beschreibung 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Hersteller DAVICOM
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Gesamt 30 Seiten
DM9331A Datasheet, Funktion
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
1. General Description
The DM9331A is a physical-layer, single-chip, low
power transceiver for media converter application. On
the media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5)
for 100BASE-TX Fast Ethernet, and it also provides
PECL interface to connect the external fiber optical
transceiver. Through the Media Converter Interface
(MCI), the DM9331A connects to another DM9331A
for the twisted pair to the fiber media converter, or
fiber to fiber repeater.
The DM9331A uses a low-power and
high-performance CMOS process. It contains the
entire physical layer functions of 100BASE-TX as
defined by IEEE802.3u, including the Physical
Coding Sublayer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium
Dependent Sublayer (TP-PMD) and a PECL
compliant interface for a fiber optical module,
compliant with ANSI X3.166. The DM9331A provides
a strong support for the auto-negotiation function,
utilizing automatic selection of full or half-duplex
mode. Furthermore, due to the built-in wave-shaping
filter, the DM9331A needs no external filter to
transport signals to the media on the 100base-TX
Ethernet operation.
2. Block Diagram
100Base-FX
PECL
Interface
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-
TX
PCS
Media
Converter
Interface
Auto-Negotiation
TX/RX Module
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
Preliminary
Version: DM9331A-DS-P02
October 7, 2008
1






DM9331A Datasheet, Funktion
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
5. Pin Description
I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output, U : Pulled up
D : Pulled down
5.1 Media Converter Interface, 18 pins
Pin No.
14
17
18
20,19
21
22
24
25
26
27
29,28
Pin Name
TPFAULT
LNKFAULT#
LNKFAULTEN
TXD [0:1]
TXEN
TXCLK
MDC
MDIO
FXFAULT/
TPSET1
TPSET0
RXD [0:1]
I/O Description
O Twisted Pair Fault
0 = Twisted pair link fault
1 = Twisted pair normal work
I Link Fault Propagation
0 = Link fault propagation is active
1 = normal operation
I Link Fault Propagation Enable
0 = Link fault propagation disable
1 = Link fault propagation enable
I Transmit Data
2-bit data inputs (synchronous to the 50MHz OSCIN)
I Transmit Enable
Active high indicates the presence of valid data on the TXD [0:1] for
100Mbps mode
O Transmit Clock
25MHz transmit clock
I Management Data Clock
Synchronous clock for the MDIO management data. This clock is
provided by management entity, and it is up to 2.5MHz
I/O Management Data I/O
Bi-directional management data that may be provided by the station
management entity or the PHY
O, Fiber Fault
Z, 0 = Fiber link fault; Fiber receive far end fault package or fiber
LI disconnect
(D) 1 = Fiber normal work
TPSET1 (reset latch input)
0 = Fiber mode; default pull low
1 = Twisted pair mode; need 10kΩ resistor to pull high
Z, Twisted Pair set (reset latch input)
LI 0 = Fiber mode; default pull low
(D) 1 = Twisted pair mode; need 10kΩ resistor to pull high
O, Receive Data Output
Z, 2-bit data outputs (synchronous to the 50MHz OSCIN)
LI Chip PHY-address of Management Register (reset latch input)
(D) RXD [0:1]
FX Mode:
TP Mode:
0,0 PHY-address =
0X00
0X0C
0,1 PHY-address =
0X01
0X0D
1,0 PHY-address =
0X02
0X0E
1,1 PHY-address =
0X03
0X0F
0 = Defaults
1 = Needs 10kΩ register to pull high
6 Preliminary
Version: DM9331A-DS-P02
October 20, 2008

6 Page









DM9331A pdf, datenblatt
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
7.2 100Base-TX Operation
The 100Base-TX transmitter receives 2-bit data clocked in
at 50MHz from the MCI, and outputs a scrambled 5-bit
encoded MLT-3 signal to the media at 100Mbps. The
on-chip clock circuit converts the 25MHz clock into a
125MHz clock for internal use.
These two busses include various controls and signal
indications that facilitate data transfers between the
DM9331A chip set.
7.2.1 100Base-TX Transmit
The 100Base-TX transmitter consists of the functional
blocks shown in figure 2. The 100Base-TX transmit section
converts 2-bits synchronous data provided by the MCI to a
scrambled MLT-3 125 million symbols per second serial
data stream.
MCI
Signals
50M OSCI
TX CGM
LED1-3#
LED
Driver
MCI
Interface/
Control
4B/5B
Encoder
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
TX±
4B/5B
Decoder
Code-
group
Alignment
25M CLK
Rise/Fall
Time
CTL
125M CLK
Descrambler
Serial to
Parallel
Digital
Logic
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
RX±
Auto-Negotiation
TX/RX Module
RX±
TX±
Register
Figure 7-2
12 Preliminary
Version: DM9331A-DS-P02
October 20, 2008

12 Page





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