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PDF DM9102H Data sheet ( Hoja de datos )
| Número de pieza | DM9102H | |
| Descripción | Single Chip Fast Ethernet NIC Controller | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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DM9102H
Single Chip Fast Ethernet NIC Controller
DAVICOM Semiconductor, Inc.
DM9102H
Single Chip Fast Ethernet
NIC Controller
DATA SHEET
Final
Version: DM9102H-12-DS-F01
February 15, 2008
Final
Version: DM9102H-DS-F01
February 15, 2008
1 page  
DM9102H
Single Chip Fast Ethernet NIC Controller
1. General Description
The DM9102H is a fully integrated and cost effective single
chip Fast Ethernet NIC controller. It is designed with low
power and high performance process. It is a 1.8V/3.3V
device with 5V tolerance.
The DM9102H provides direct interface to the PCI bus and
supports bus master mode to achieve the high performance
of the PCI bus. It fully complies with PCI 2.2. In the media
side, the DM9102H interfaces to the UTP3, 4, 5 in 10Base-T
and the UTP5 in 100Base-TX. It is fully compliant with the
IEEE 802.3u Spec. Its auto-negotiation function will
automatically configure the DM9102H to take the maximum
advantage of its abilities. The DM9102H also supports IEEE
802.3x’s full-duplex flow control.
The DM9102H supports two types of power management
mechanisms. The main mechanism is based on the On
Now architecture, which is required for PC99. The
alternative mechanism is based upon the remote
Wake-On-LAN mechanism.
2. Block Diagram
TX+/-
RX+/-
NRZI to MLT3
PHYceiver
NRZ to NRZI
Parallel to
Serial
AEQ
MLT3 to NRZI
NRZI to NRZ
Serial to
Parallel
EEPROM
Interface
Boot ROM /
MII Interface
DMA
Scrambler
4B/5B
Encoding
De-
Scrambler
4B/5B
Decoding
MAC
TX
Machine
TX
FIFO
MII
RX
Machine
RX
FIFO
PCI
Interface
LED Driver
Autonegotiation
MII Management Control
& MII Register
Power
Management
Block
PME#
WOL
Final
Version: DM9102H-12-DS-F01
February 15, 2008
2
5 Page 
5.5 Miscellaneous Pins
Pin No.
128LQFP
36
71
37
94
97
98
102
101
116
95
Pin Name
CLOCKRUN#
TEST2
TEST1
WOL
X2
X1/OSC
BGRES
BGRESG
ISOLATE#
VCTRL18
DM9102H
Single Chip Fast Ethernet NIC Controller
I/O Description
I/O, Clockrun#
O/D The clockrun# signal is used by the system to pause or slow
down the PCI clock signal. It is used by the DM9102H to
enable or disable suspension of the PCI clock signal or restart
of the PCI clock. When the clockrun# signal is not used, this pin
should be connected to an external pulled down resistor.
I TEST mode control 2
In normal operation, this pin is pulled high.
I TEST Mode Control 1
In normal operation, this pin is pulled low.
O Wake up signal. The DM9102H can assert this pin if it detects
link status change, magic packet, or sample frame. The default
is “normal low, active high pulse”. DM9102H also supports
High/Low and Pulse/Level options.
O Crystal feedback output pin is used for crystal connection only.
Leave this pin open if oscillator is used.
I Crystal or Oscillator Input. (25MHz±30ppm)
25MHz Oscillator or series resonance, fundamental
frequency crystal.
I Band gap Voltage Reference Resistor.
It connects to a 6.8KΩ1% error tolerance resistor between this
pin and BGRESG pin, to provide an accurate current reference
for DM9102H (10Base-T/100Base-TX Application).
I For Band gap Circuit
It is used together with the BGRES pin.
I Isolate
This isolate signal is used to isolate the DM9102H from the
system, and it is suitable for LAN on motherboard. When
isolate signal is active low, it disables the DM9102H function
and the DM9102H will not drive any outputs and sample any
inputs. In this case, the power consumption is minimum.
O Voltage 1.8V control
This pin can be used to control a BJT transistor‘s base pin to
generate a stable 1.8V power in BJT’s collect pin.
Final
Version: DM9102H-12-DS-F01
February 15, 2008
6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9102H.PDF ] | |
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