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PDF DM9010BI Data sheet ( Hoja de datos )
| Número de pieza | DM9010BI | |
| Descripción | Industrial-temperature 10/100 MbpsSingle Chip Ethernet Controller | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9010BI
Industrial-temperature 10/100 Mbps Single Chip
Ethernet Controller
With General Processor Interface
DATA SHEET
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Preliminary
Version: DM9010BI-DS-P01
January 12, 2010
1
1 page  
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
1. GENERAL DESCRIPTION
The DM9010BI is a fully integrated and cost-effective
Industrial-temperature single chip Fast Ethernet MAC
controller with a general processor interface, a
10/100M PHY and 16K Byte SRAM. It is designed
with low power and high performance process that
support 3.3V with 5V tolerance.
The DM9010BI also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface.
The DM9010BI supports 8-bit, 16-bit and 32-bit uP
interfaces to internal memory accesses for different
processors. The PHY of the DM9010BI can interface to
the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX. It is
fully compliant with the IEEE 802.3u Spec. Its
auto-negotiation function will automatically configure the
DM9010BI to take the maximum advantage of its abilities.
The DM9010BI also supports IEEE 802.3x full- duplex flow
control. This programming of the DM9010BI is very simple,
so user can port the software drivers to any system easily.
2. BLOCK DIAGRAM
LED
External MII
Interface
EEPROM
Interface
TX+/-
RX +/-
PHYceiver
100Base TX-
transceiver
100 Base- TX
PCS
Auto -
MDIX
10 Base T
Tx R/x
MAC
TX Machine
MII
Control &Status
Registers
RX Machine
Memory
Management
Autonegotiation
MII Management
Control
& MII Register
Internal
SRAM
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
5
5 Page 
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5.3 EEPROM Interface
64 EEDI
I Data from EEPROM
65
EEDO
O,PD Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WOL, and it
can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKE EEDO data width
0 0 16-bit
0 1 32-bit
1 0 8-bit
1 1 reserved
66
EECK
O,PD Clock to EEPROM
67
EECS
O,PD Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS, EECK and EEDO are all have a pulled down resistor about 60 k ohms internally
5.4 Clock Interface
21 X2_25M
22 X1_25M
59 CLK20MO
O Crystal 25MHz Out
I Crystal 25MHz In
I/O,PD 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
When pin TEST5 state is high, this pin acts as the system clock.
5.5 LED Interface
60 SPLED
61 FDLED
62 LKLED
O Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
O Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
O Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9010BI.PDF ] | |
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