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DM9621A Schematic ( PDF Datasheet ) - DAVICOM

Teilenummer DM9621A
Beschreibung USB2.0 to 10/100M Fast Ethernet Controller
Hersteller DAVICOM
Logo DAVICOM Logo 




Gesamt 30 Seiten
DM9621A Datasheet, Funktion
DM9621A
USB2.0 to Fast Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9621A
USB2.0 to 10/100M Fast Ethernet Controller
DATA SHEET
Final
Doc No: DM9621A-13-MCO-DS-F01
June 30, 2015
Final
Version: DM9621A-13-MCO-DS-F01
June 30, 2015
1






DM9621A Datasheet, Funktion
DM9621A
USB2.0 to Fast Ethernet Controller
l LED Indications
§ Ethernet – Link / Act indication
§ Ethernet – Speed (10M / 100M) indication
§ USB speed indication (full / high speed + traffic modes)
l Clock
§ Single 25MHz / 30 ppm crystal or oscillator
§ Optional 12MHz crystal for USB
l Power Input
§ Low-Power, Single-Supply 3.3V, 0.18um CMOS Technology
§ Built in 3.3V to 1.8V regulator
l Miscellaneous
§ Very low power consumption in suspend mode
§ Power Reduced Mode (cable detection), and Power Down Mode
§ Compatible with 5.0V tolerant I/O
1.1 General Description
The DM9621A USB to 10/100Mbps Fast Ethernet controller is a high performance and highly integrated ASIC
with embedded SSRAM for packet buffering. It enables low cost and affordable Fast Ethernet network
connection to desktop, notebook PC, and embedded system using popular USB ports.
It has an USB interface to communicate with USB host controller and is compliant with USB specification V1.0,
V1.1 and V2.0. It implements 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u
standards.
DM9621A integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an
optional Reduce media-independent interface (RMII).
Final
Doc No: DM9621A-13-MCO-DS-F01
June 30, 2015
6

6 Page









DM9621A pdf, datenblatt
DM9621A
USB2.0 to Fast Ethernet Controller
4 Vender Control an Status Register Set
The DM9621A implements several control and status registers, which can be accessed by the USB vendor
register type commands. All CRs are set to their default values by hardware or software reset unless
otherwise specified.
Register
Description
Offset
Default value
after reset
NCR
Network Control Register
00H 00H
NSR
Network Status Register
01H 00H
TCR
TX Control Register
02H 00H
RCR
RX Control Register
05H 00H
RSR
RX Status Register
06H 00H
ROCR
Receive Overflow Counter Register
07H 00H
BPTR
Back Pressure Threshold Register
08H 37H
FCTR
Flow Control Threshold Register
09H 38H
FCR
RX Flow Control Register
0AH 00H
EPCR
EEPROM & PHY Control Register
0BH 00H
EPAR
EEPROM & PHY Address Register
0CH 40H
EPDRL
EEPROM & PHY Low Byte Data Register
0DH
Unknown
EPDRH
EEPROM & PHY High Byte Data Register
0EH
Unknown
WCR
Wake Up Control Register
0FH 00H
PAR Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Register
16H-1DH
000000000000
0080
GPCR
General Purpose Control Register
1EH 01H
GPR
General Purpose Register
1FH Unknown
VID Vendor ID
28H-29H
0A46H
PID Product ID
2AH-2BH
9621H
CHIPR
CHIP revision
2CH 01H
TSCR
TX Special Control Register
2DH 00H
TCSCR
Transmit Check Sum Control Register
31H
00H
RCSCSR
Receive Check Sum Control Status Register
32H
00H
GPCR2
General Purpose Control Register 2
34H 00H
GPR2
General Purpose Register 2
35H 00H
EEP_CTRL EEPROM and PHY Control Register
3AH 00H
PPCSR
Pause Packet Control Status Register
3DH
04H
TX_CTR
Transmit Packet Counter
81H 00H
UPERR
USB Packet Error Counter
82H 00H
CRC_CTR Ethernet Receive Packet CRC Error Counter
83H
00H
EXCOL_CT Ethernet Transmit Excessive Collision Counter
R
84H
00H
COL_CTR Ethernet Transmit Collision Counter
85H 00H
LCOL_CTR Ethernet Transmit Late Collision Counter
86H
00H
MODE_CTL Mode Control
91H 00H
SQUELCH USB squelch Control
95H 04H
USB_ADR USB Address
96H 00H
USBDA
USB device address register
F0H 00H
RXC
Received packet counter register
F1H 00H
TXC/USBS Transmit packet counter/USB status register
F2H
10H
USBC
USB control register
F4H 00H
Final
Doc No: DM9621A-13-MCO-DS-F01
June 30, 2015
12

12 Page





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