PDF DM9000 Data sheet ( Hoja de datos )

Número de pieza	DM9000
Descripción	ISA to Ethernet MAC Controller
Fabricantes	Davicom
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No Preview Available ! 1. General Description DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY The DM9000 is a fully integrated and cost-effective single chip Fast Ethernet MAC controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM. It is designed with low power and high performance process that support 3.3V with 5V tolerance. The DM9000 also provides a MII interface to connect HPNA device or other transceivers that support MII interface. The DM9000 supports 8-bit, 16-bit and 32-bit uP interfaces to internal memory accesses for different processors. The PHY of the DM9000 can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX. It is fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000 to take the maximum advantage of its abilities. The DM9000 also supports IEEE 802.3x full- duplex flow control. This programming of the DM9000 is very simple, so user can port the software drivers to any system easily. 2. Block Diagram TX+/- RX+/- LED External MII Interface EEPROM Interface PHYceiver 100 Base-TX transceiver 100 Base-TX PCS 10 Base-T Tx/Rx MAC TX Machine MII Control &Status Registers RX Machine Memory Management Autonegotiation MII Management Control & MII Register Internal SRAM Final Version: DM9000-DS-F03 April 23, 2009 1 1 page DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 4. Pin Configuration 4.1 Pin Configuration I: with MII Interface DGND NC LINK_O WAKEUP PW_RST# DGND SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 DVDD IO16 DATA/ADR# SA4 SA5 SA6 SA7 SA8 SA9 DGND INT 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DM9000 50 TXD0 49 TX_CLK 48 TEST5 47 RX_CLK 46 RX_ER 45 RX_DV 44 COL 43 CRS 42 DGND 41 RXD3 40 RXD2 39 RXD1 38 RXD0 37 LINK_I 36 DVDD 35 AVDD 34 TXO- 33 TXO+ 32 AGND 31 AGND 30 RX- 29 RX+ 28 AVDD 27 AVDD 26 BGRES Final Version: DM9000-DS-F03 April 23, 2009 5 5 Page DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6. Vendor Control and Status Register Set The DM9000 implements several control and status registers, which can be accessed by the host. These CSRs are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are specified Register Description Offset NCR NSR TCR TSR I TSR II RCR RSR ROCR BPTR FCTR FCR EPCR EPAR EPDRL EPDRH WCR PAR Network Control Register Network Status Register TX Control Register TX Status Register I TX Status Register II RX Control Register RX Status Register Receive Overflow Counter Register Back Pressure Threshold Register Flow Control Threshold Register RX Flow Control Register EEPROM & PHY Control Register EEPROM & PHY Address Register EEPROM & PHY Low Byte Data Register EEPROM & PHY High Byte Data Register Wake Up Control Register Physical Address Register 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H-15H MAR GPCR GPR TRPAL TRPAH RWPAL RWPAH VID PID CHIPR SMCR MRCMDX MRCMD MRRL MRRH MWCMDX MWCMD MWRL Multicast Address Register General Purpose Control Register General Purpose Register TX SRAM Read Pointer Address Low Byte TX SRAM Read Pointer Address High Byte RX SRAM Write Pointer Address Low Byte RX SRAM Write Pointer Address High Byte Vendor ID Product ID CHIP Revision Special Mode Control Register Memory Data Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read_ address Register Low Byte Memory Data Read_ address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write_ address Register Low Byte 16H-1DH 1EH 1FH 22H 23H 24H 25H 28H-29H 2AH-2BH 2CH 2FH F0H F2H F4H F5H F6H F8H FAH Final Version: DM9000-DS-F03 April 23, 2009 Default value after reset 00H 00H 00H 00H 00H 00H 00H 00H 37H 38H 00H 00H 40H XXH XXH 00H Determined by EEPROM XXH 01H XXH 00H 00H 04H 0CH 0A46H 9000H 00H 00H XXH XXH 00H 00H XXH XXH 00H 11 11 Page

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