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PDF DM9051I Data sheet ( Hoja de datos )
| Número de pieza | DM9051I | |
| Descripción | SPI to Ethernet Controller | |
| Fabricantes | DAVICOM | |
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DM9051(I)
SPI to Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9051(I)
SPI to Ethernet Controller
DATA SHEET
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Version: DM9051(I)-12-MCO-DS-P01
March 30, 2015
1
1 page  
DM9051(I)
SPI to Ethernet Controller
1 General Description
The DM9051(I) is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a
Serial Peripheral Interface (SPI), a 10/100M PHY and MAC, and 16K-byte SRAM. It is designed with low
power and high performance process interface that support 3.3V with 5V IO tolerance.
The PHY of the DM9051(I) can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP
Auto-MDIX.It is fully compliant with the IEEE 802.3u Spec. Its Auto-Negotiation function will automatically
configure the DM9051(I) to take the maximum advantage of its 10M or 100M abilities.
The DM9051(I) supports IEEE 802.3az in PHY and MAC to save power consumption when Ethernet is idle.
The IEEE 802.3x Full-Duplex flow control and Half-Duplex back-pressure function also supported to avoid
Ethernet packet loss with link partner.
The slave SPI interface is designed to support SPI clock mode 0 and 3 that compatible with the all master SPI
interface of CPU. The clock speed can up to 50Mhz to co-operation with most high throughput master SPI.
The SPI burst command format is code-effective to minimize the command overhead in access DM9051(I)
internal registers and packet data in memory.
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
5
5 Page 
5.6 Miscellaneous
Pin No.
Pin Name
9 TEST3
10 GP1
14 WOL
22 TEST2
23 GP2
27 RSTB
28 GP3
DM9051(I)
SPI to Ethernet Controller
Type
I,PD
I/O
O,PD
Description
Operation Mode
Force to high in normal application
General Purpose Pin 1
This is a general purpose pin controlled by bit 1 of MAC register
1EH/1FH.
Wake On Lan
This is a control signal when wake up event occurred.
I,PD
I/O
I
Its polarity and output type can be controlled by EEPROM
setting.
Operation Mode
Force to ground in normal application
General Purpose Pin 2
This is a general purpose pin controlled by bit 2 of MAC register
1EH/1FH.
Power on Reset
Active low signal to initiate the DM9051(I).
I/O,PD
The DM9051(I) is ready after 5us when this pin disserted.
General Purpose Pin 3
This is a general purpose pin controlled by bit 3 of MAC register
1EH/1FH.
5.7 Power Pins
Pin No.
Pin Name
15,21,29
VDD33
33 VSS
Type
P
P
Description
VDD
3.3V power input
The QFN package ground
5.8 Strap Pins
Pin No.
Pin Name
Description
12
EECK
Polarity of INT
1 = INT pin low active
0 = INT pin high active
13
EECS
BIST Control
1 = Enable BIST
0 = Disable BIST
14
WOL
INT Output Type
1 = Open-Drain
0 = Push-pull mode
Note: If memory BIST function is enabled, the SPI interface should not active before RSTB go high 2ms.
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9051I.PDF ] | |
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