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DM9051 Schematic ( PDF Datasheet ) - DAVICOM

Teilenummer DM9051
Beschreibung SPI to Ethernet Controller
Hersteller DAVICOM
Logo DAVICOM Logo 




Gesamt 30 Seiten
DM9051 Datasheet, Funktion
DM9051(I)
SPI to Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9051(I)
SPI to Ethernet Controller
DATA SHEET
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
Version: DM9051(I)-12-MCO-DS-P01
March 30, 2015
1






DM9051 Datasheet, Funktion
DM9051(I)
SPI to Ethernet Controller
2 Features
l Slave SPI Interface with clock speeds up to 50MHz for high throughput applications
l Support SPI clock mode 0 and 3
l Support 10BASE-T and 100BASE-TX and 100M Fiber interface
l Support HP Auto-MDIX crossover function in 10BASE-T and 100BASE-TX
l Support IEEE 802.3az Energy Efficient Ethernet (EEE)
l Support interface for EEPROM to configure chip settings
l Support back pressure flow control for Half-Duplex mode
l Support IEEE802.3x flow control for Full-Duplex mode
l Supports wakeup frame, link status change and magic packet events to generate
remote wake on LAN (WOL) signal
l Support IPv4/ TCP / UDP checksum generation and checking
l Configurable of internal transmit/receive buffers within 16K-byte memory
l Built-in integrated 3.3V to 1.8V low noise regulator for core and analog blocks
l Support EMI (Class B) and HBM ESD Rating 8KV
l Support Industrial Temperature Range: –40to +85(DM9051I)
l 3.3V I/O with 5V tolerant
l DSP architecture PHY Transceiver
l 0.18um process
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
6

6 Page









DM9051 pdf, datenblatt
DM9051(I)
SPI to Ethernet Controller
6 MAC Control and Status Register Set
The DM9051(I) implements several control and status registers, which can be accessed by the host. These
CSRs are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are
specified.
Register
Description
Offset
Default Value
after Reset
NCR
Network Control Register
00H 00H
NSR
Network Status Register
01H 00H
TCR
TX Control Register
02H 00H
TSR I
TX Status Register I
03H 00H
TSR II
TX Status Register II
04H 00H
RCR
RX Control Register
05H 00H
RSR
RX Status Register
06H 00H
ROCR Receive Overflow Counter Register
07H 00H
BPTR
Back Pressure Threshold Register
08H 37H
FCTR
Flow Control Threshold Register
09H 38H
FCR
RX/TX Flow Control Register
0AH 00H
EPCR
EEPROM & PHY Control Register
0BH 00H
EPAR
EEPROM & PHY Address Register
0CH 40H
EPDRL EEPROM & PHY Low Byte Data Register
0DH XXH
EPDRH EEPROM & PHY High Byte Data Register
0EH XXH
WCR
Wake Up Control Register
0FH 00H
PAR
Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Hash Table Register
16H-1DH
XXH
GPCR General Purpose Control Register
1EH 71H
GPR
General Purpose Register
1FH XXH
TRPAL TX Memory Read Pointer Address Low Byte
22H 00H
TRPAH TX Memory Read Pointer Address High Byte
23H 00H
RWPAL RX Memory Write Pointer Address Low Byte
24H 00H
RWPAH RX Memory Write Pointer Address High Byte
25H 0CH
VID Vendor ID
28H-29H
0A46H
PID Product ID
2AH-2BH
9051H
CHIPR CHIP Revision
2CH 01H
TCR2
Transmit Control Register 2
2DH 00H
ATCR
Auto-Transmit Control Register
30H 00H
TCSCR Transmit Check Sum Control Register
31H 00H
RCSCSR Receive Check Sum Control Status Register
32H 00H
SBCR
SPI Bus Control Register
38H 44H
INTCR INT Pin Control Register
39H 00H
PPCSR Pause Packet Control Status Register
3DH 01H
EEE_IN IEEE 802.3az Enter Counter Register
3EH 05H
EEE_OUT IEEE 802.3az Leave Counter Register
3FH 0FH
ALNCR SPI Byte Align Error Counter Register
4AH 00H
RLENCR RX Packet Length Control Register
52H 00H
BCASTCR RX Broadcast Control Register
53H 00H
INTCKCR INT Pin Clock Output Control Register
54H 00H
MPTRCR Memory Pointer Control Register
55H 00H
MLEDCR More LED Control Register
57H 00H
MEMSCR Memory Control Register
59H 00H
TMEMR Transmit Memory Size Register
5AH 03H
MBSR Memory BIST Status Register
5DH 40H
Doc No: DM9051(I)-12-MCO-DS-P01
March 30, 2015
12

12 Page





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