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PDF DM54191 Data sheet ( Hoja de datos )
| Número de pieza | DM54191 | |
| Descripción | Synchronous Up/Down 4-Bit Binary Counter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1989
54191 DM54191 DM74191 Synchronous Up Down
4-Bit Binary Counter with Mode Control
General Description
This circuit is a synchronous reversible up down counter
The 191 is a 4-bit binary counter Synchronous operation is
provided by having all flip-flops clocked simultaneously so
that the outputs change simultaneously when so instructed
by the steering logic This mode of operation eliminates the
output counting spikes normally associated with asynchro-
nous (ripple clock) counters
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input if the
enable input is low A high at the enable input inhibits count-
ing Level changes at either the enable input or the down
up input should be made only when the clock input is high
The direction of the count is determined by the level of the
down up input When low the counter counts up and when
high it counts down
This counter is fully programmable that is the outputs may
be preset to either level by placing a low on the load input
and entering the desired data at the data inputs The output
will change independent of the level of the clock input This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs
The clock down up and load inputs are buffered to lower
the drive requirement which significantly reduces the num-
ber of clock drivers etc required for long parallel words
Two outputs have been made available to perform the cas-
cading function ripple clock and maximum minimum count
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used or to the clock input if parallel enabling is used The
maximum minimum count output can be used to accom-
plish look-ahead for high-speed operation
Features
Y Single down up count control line
Y Count enable control input
Y Ripple clock output for cascading
Y Asynchronously presettable with load control
Y Parallel outputs
Y Cascadable for n-bit applications
Y Alternate Military Aerospace device (54191) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
Order Number 54191DMQB 54191FMQB
DM54191J DM54191W or DM74191N
See NS Package Number J16A N16E or W16A
TL F 6562 – 1
C1995 National Semiconductor Corporation TL F 6562
RRD-B30M105 Printed in U S A
1 page  
Timing Diagrams
191 Decade Counter
Typical Load Count and Inhibit Sequences
Physical Dimensions inches (millimeters)
TL F 6562 – 3
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54191DMQB or DM54191J
NS Package Number J16A
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DM54191.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DM54191 | Synchronous Up/Down 4-Bit Binary Counter | National Semiconductor |
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