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CHZ180A-SEB Schematic ( PDF Datasheet ) - United Monolithic Semiconductors

Teilenummer CHZ180A-SEB
Beschreibung 180W L-Band HPA
Hersteller United Monolithic Semiconductors
Logo United Monolithic Semiconductors Logo 




Gesamt 14 Seiten
CHZ180A-SEB Datasheet, Funktion
CHZ180A-SEB
180W L-Band HPA
GaN HEMT on SiC in SEB Package
Description
The CHZ180A-SEB is an input matched and
output pre-matched packaged Gallium Nitride
High Electron Mobility Transistor. It allows
broadband solutions for a variety of RF
power applications in L-band. It is well suited
for pulsed radar application.
The CHZ180A-SEB is proposed on a 0.5µm
gate length GaN HEMT process. It is based
on Quasi-MMIC technology.
It is available in a hermetic flange ceramic
metal power package providing low parasitic
and low thermal resistance.
Main Features
Wide band capability: 1.2 1.4GHz
Pulsed operating mode
High power: > 180W
High PAE: up to 53%
DC bias: VDS = 45V @ ID_Q = 1.3A
MTTF > 106 hours @ Tj = 200°C
RoHS Hermetic Flange Ceramic package
VDS = 45V, ID_Q = 1.3A, Pin = 39dBm
Pulsed mode (100µs-10%)
60 25
58
Pulsed Mode
24
56
54 POUT
23
22
52 21
50 20
48
46
PAE
19
18
44 17
42 16
40 15
38
Gain
14
36 13
34 12
32 11
30
1
10
1.1 1.2 1.3 1.4 1.5 1.6
Frequency (GHz)
Performances given at the connector access
planes.
Main Electrical Characteristics
Tamb. = +25°C, Pulsed mode
Symbol
Parameter
Freq Frequency range
GSS
PSAT
PAEmax
Small Signal Gain
Saturated Output Power
Max Power Added Efficiency
IDSAT Saturated Drain Current
Min Typ Max Unit
1.2 1.4 GHz
20 dB
52 53 54 dBm
45 52
%
9A
Ref. : DSCHZ180A-SEB4065 - 06 Mar 14
1/14 Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34






CHZ180A-SEB Datasheet, Funktion
CHZ180A-SEB
180W L-Band HPA
Typical Performance on Evaluation Board (Ref. 61501354)
Tcase = +25°C, Pulsed mode (1). Measured on the connector access planes.
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
0
S Parameters
VDS = 45V, ID_Q = 1.3A
S(2,1)
S(1,1)
S(2,2)
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency (GHz)
2.2 2.4 2.6 2.8
3
(1) Input RF and gate voltage are pulsed. Conditions are 100µs width, 10% duty cycle and 1µs
offset between DC and RF pulse
Ref. : DSCHZ180A-SEB4065 - 06 Mar 14
6/14 Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34

6 Page









CHZ180A-SEB pdf, datenblatt
CHZ180A-SEB
180W L-Band HPA
Recommended Assembly Procedure
CHZ180A-SEB is available as a flange package to be bolted down onto a thermal heat sink
also used as main electrical ground. Use preferably screw M2 and flat washers.
Thermal and electrical resistance at the package to heat sink interface has to be as low as
possible. Thermal electrically conductive grease or conductive thin layer like indium sheets
are recommended between the package and the heat sink.
In case a thermal grease is selected, we recommend to use material offering thermal
conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness
should be about 25µm (1 mil).
Contact interface quality can be improved by cleaning process prior device mounting on the
heat-sink. Such operation will enhance the thermal and electrical contact by oxide removal at
each interface.
Package leads can be soldered on printed circuit board traces by using RoHS solder past.
Cavity depth and width to be performed into the heat-sink where the device will be mounted
are important to achieve the best performances. These dimensions have to be optimized in
order to minimize the distance between device and signal traces made on the printed circuit
board (PCB). But they also have to be calculated in order to accommodate device variations
in height. The following drawing gives the relationship between device dimensions (Hpack &
Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed circuit-
board configuration (HPCB)
Ref. : DSCHZ180A-SEB4065 - 06 Mar 14
12/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34

12 Page





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