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82P33810 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 82P33810
Beschreibung Synchronization Management Unit
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 13 Seiten
82P33810 Datasheet, Funktion
Synchronization Management Unit for
IEEE 1588 and Synchronous Ethernet
82P33810
Short Form Datasheet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on
the last page.
HIGHLIGHTS
• Synchronization Management Unit (SMU) provides tools to manage
physical layer and packet based synchronous clocks for IEEE 1588 /
PTP Telecom Profile applications
• Supports independent IEEE 1588 and Synchronous Ethernet
(SyncE) timing paths
• Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time
Slave Clocks (T-TSC) per G.8273.2
• Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally
Controlled Oscillators (DCOs) for PTP clock synthesis
• DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
• DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
• Two independent Time of Day (ToD) counters/time accumulators, one
associated with each of DPLL1 and DPLL2, can be used to track dif-
ferences between the two time domains and to time-stamp external
events
• DPLL3 performs rate conversions to frequency synchronization inter-
faces or for other general purpose timing applications
• APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X
• Fractional-N input dividers support a wide range of reference fre-
quencies
• Locks to 1 Pulse Per Second (PPS) references
• It can be configured from an external EEPROM after reset
FEATURES
• Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization
interface signals per ITU-T G.703
• Differential reference inputs (IN3 to IN8) accept clock frequencies
between 1 PPS and 650 MHz
• Single ended inputs (IN9 to IN14) accept reference clock frequencies
between 1 PPS and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
• Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
• Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G
Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS
frequencies
• Any reference input (IN3 to IN14) can be designated as external sync
pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-
able reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
• DPLL1 and DPLL2 can be configured with bandwidths between 0.09
mHz and 567 Hz
• DPLL1 and DPLL2 lock to input references with frequencies between
1 PPS and 650 MHz
• DPLL3 locks to input references with frequencies between 8 kHz and
650 MHz
• DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous
Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equip-
ment Clock (SEC); and Telcordia GR-253-CORE for Stratum 3 and
SONET Minimum Clock (SMC)
• DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1 and OUT8
• DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
• DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT10 and OUT11
• APLL1 and APLL2 can be connected to DPLL1 or DPLL2
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
• Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave, SPI or the UART interface can be used by a host pro-
cessor to access the control and status registers
• The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset
• DPLL1 or DPLL3 can be connected to an internal composite clock
generator that outputs its 64 kHz synchronization signal on OUT8
• Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
• Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks
with frequencies between 1 PPS and 125 MHz
• Single ended outputs OUT10 and OUT11 output clocks N*8kHz multi-
ples up to 100 MHz
• DPLL1 and DPLL2 support independent programmable delays for
each of IN3 to IN14; the delay for each input is programmable in
steps of 0.61 ns with a range of ~±78 ns
• The input to output phase delay of DPLL1 and DPLL2 is programma-
ble in steps of 0.0745 ps with a total range of ±20 μs
• The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT8 is individually programmable in steps of ~200 ps
with a total range of +/-180°
• 1149.1 JTAG Boundary Scan
• 144-pin CABGA green package
©2016 Integrated Device Technology, Inc.
1
Revision 6, March 29, 2016






82P33810 Datasheet, Funktion
82P33810 Short Form Datasheet
Table 1: Pin Description (Continued)
Pin No.
J10
H10
G10
F10
E11
E10
E12
C12
L8
K5
M5
M6
M1
M2
A6
B6
A8
B8
C4
C10
M9
M10
D12
D11
C9, A9, D8
E9
G9
H9
Name
IN9
IN10
IN11
IN12
IN13
IN14
FRSYNC
_8K_1PPS
MFRSYNC
_2K_1PPS
OUT1
OUT2
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OUT8
OUT9_POS
OUT9_NEG
OUT10
OUT11
CAP1, CAP2,
CAP3
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
I/O
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
O
O
O
Type Description
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
IN9: Input Clock 9
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN10: Input Clock 10
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN11: Input Clock 11
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN12: Input Clock 12
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN13: Input Clock 13
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN14: Input Clock 14
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
Output Frame Synchronization Signal
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
CMOS OUT1 ~ OUT2: Output Clock 1 ~ 2
O
PECL/LVDS
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O CMOS OUT7 ~ OUT8: Output Clock 7 ~ 8
OUT9_POS / OUT9_NEG: Positive / Negative Output Composite Clock
O AMI A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
O CMOS OUT10 ~ OUT11: Output Clock 10 ~ 11
Miscellaneous
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors
are be part of the power filtering.
Lock Signal
O
CMOS
DPLL3_LOCK
This pin goes high when DPLL3 is locked
O
CMOS
DPLL2_LOCK
This pin goes high when DPLL2 is locked
O
CMOS
DPLL1_LOCK
This pin goes high when DPLL1 is locked
©2016 Integrated Device Technology, Inc.
6
Revision 6, March 29, 2016

6 Page









82P33810 pdf, datenblatt
82P33810 Short Form Datasheet
ORDERING INFORMATION
Table 2: Ordering Information
Part/Order Number
82P33810ABAG
82P33810ABAG8
Package
144-pin CABGA green package
144-pin CABGA green package
Shipping Packaging
Tray
Tape & Reel
"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Temperature
-40o to +85oC
-40o to +85oC
©2016 Integrated Device Technology, Inc.
12
Revision 6, March 29, 2016

12 Page





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