|
|
Teilenummer | 82P33814 |
|
Beschreibung | Synchronization Management Unit | |
Hersteller | Integrated Device Technology | |
Logo | ||
Gesamt 13 Seiten Synchronization Management Unit for
IEEE 1588 and Synchronous Ethernet
82P33814
Short Form Datasheet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on
the last page.
HIGHLIGHTS
• Synchronization Management Unit (SMU) provides tools to manage
physical layer and packet based synchronous clocks for IEEE 1588 /
PTP Telecom Profile applications
• Supports independent IEEE 1588 and Synchronous Ethernet
(SyncE) timing paths
• Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time
Slave Clocks (T-TSC) per G.8273.2
• Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally
Controlled Oscillators (DCOs) for PTP clock synthesis
• DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
• DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
• Two independent Time of Day (ToD) counters/time accumulators, one
associated with each of DPLL1 and DPLL2, can be used to track dif-
ferences between the two time domains and to time-stamp external
events
• DPLL3 performs rate conversions to frequency synchronization inter-
faces or for other general purpose timing applications
• APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X
• Fractional-N input dividers support a wide range of reference fre-
quencies
• Locks to 1 Pulse Per Second (PPS) references
• It can be configured from an external EEPROM after reset
FEATURES
• Differential reference inputs (IN1 to IN4) accept clock frequencies
between 1 PPS and 650 MHz
• Single ended inputs (IN5 to IN6) accept reference clock frequencies
between 1 PPS and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
• Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
• Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G
Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS
frequencies
• Any reference input (IN1 to IN6) can be designated as external sync
pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-
able reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
• DPLL1 and DPLL2 can be configured with bandwidths between 0.09
mHz and 567 Hz
• DPLL1 and DPLL2 lock to input references with frequencies between
1 PPS and 650 MHz
• DPLL3 locks to input references with frequencies between 8 kHz and
650 MHz
• DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous
Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equip-
ment Clock (SEC); and Telcordia GR-253-CORE for Stratum 3 and
SONET Minimum Clock (SMC)
• DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1 and OUT8
• DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
• DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT9 and OUT10
• APLL1 and APLL2 can be connected to DPLL1 or DPLL2
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
• Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave, SPI or the UART interface can be used by a host pro-
cessor to access the control and status registers
• The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset
• Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
• Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks
with frequencies between 1 PPS and 125 MHz
• Single ended outputs OUT9 and OUT10 output clocks N*8kHz multi-
ples up to 100 MHz
• DPLL1 and DPLL2 support independent programmable delays for
each of IN1 to IN6; the delay for each input is programmable in steps
of 0.61 ns with a range of ~±78 ns
• The input to output phase delay of DPLL1 and DPLL2 is programma-
ble in steps of 0.0745 ps with a total range of ±20 μs
• The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT8 is individually programmable in steps of ~200 ps
with a total range of +/-180°
• 1149.1 JTAG Boundary Scan
• 72-pin QFN green package
APPLICATIONS
• Access routers, edge routers, core routers
• Carrier Ethernet switches
• Multiservice access platforms
• PON OLT
• LTE eNodeB
• IEEE 1588 / PTP Telecom Profile clock synthesizer
• ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom Time
Slave Clock (T-TSC)
• ITU-T G.8264 Synchronous Equipment Timing Source (SETS)
• ITU-T G.8263 Packet-based Equipment Clock (PEC)
• ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)
• ITU-T G.813 Synchronous Equipment Clock (SEC)
• Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Minimum
Clock (SMC)
©2016 Integrated Device Technology, Inc.
1
Revision 6, March 24, 2016
82P33814 Short Form Datasheet
Table 1: Pin Description (Continued)
Pin No.
30
28
25
26
21
22
71
70
68
67
65
63
61
60
13
1
54
56
55
57
46
45
47
Name
I/O Type
Description
Output Clock
OUT1
OUT2
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OUT8
OUT9
OUT10
VC1
VC2
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
O CMOS OUT1 ~ OUT2: Output Clock 1 ~ 2
O
PECL/LVDS
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O CMOS OUT7 ~ OUT8: Output Clock 7 ~ 8
O CMOS OUT9 ~ OUT10: Output Clock 9 ~ 10
Miscellaneous
VC1: APLL1 VC Output
O Analog An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
VC2: APLL2 VC Output
O Analog An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
Lock Signal
O
CMOS
DPLL3_LOCK
This pin goes high when DPLL3 is locked
O
CMOS
DPLL2_LOCK
This pin goes high when DPLL2 is locked
O
CMOS
DPLL1_LOCK
This pin goes high when DPLL1 is locked
Microprocessor Interface
INT_REQ
MPU_MODE1/
I2CM_SCL
MPU_MODE0/
I2CM_SDA
O
Tri-state
I/O
pull-down
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
CMOS/
Open Drain
01: SPI mode
10: UART mode
11: I2C master (EEPROM) mode
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
SDI/I2C_AD2/
I
UART_RX pull-down
CMOS
I2C_AD2: Device Address Bit 2
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
UART_RX
In UART mode, this pin is used as the receive data (UART Receive)
©2016 Integrated Device Technology, Inc.
6
Revision 6, March 24, 2016
6 Page 82P33814 Short Form Datasheet
ORDERING INFORMATION
Table 2: Ordering Information
Part/Order Number
82P33814ANLG
82P33814ANLG8
82P33814ANLG/W
Package
72-pin QFN green package
72-pin QFN green package
72-pin QFN green package
Shipping Packaging
Tray
Tape & Reel, Pin 1 Orientation: EIA-481-C
Tape & Reel, Pin 1 Orientation: EIA-481-D
"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Temperature
-40o to +85oC
-40o to +85oC
-40o to +85oC
Table 3: Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
NLG8
Quadrant 1 (EIA-481-C)
NLG/W
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
Correct Pin 1 ORIENTATION
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
USER DIRECTION OF FEED
©2016 Integrated Device Technology, Inc.
12
Revision 6, March 24, 2016
12 Page | ||
Seiten | Gesamt 13 Seiten | |
PDF Download | [ 82P33814 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
82P33810 | Synchronization Management Unit | Integrated Device Technology |
82P33813 | Synchronization Management Unit | Integrated Device Technology |
82P33814 | Synchronization Management Unit | Integrated Device Technology |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |