Datenblatt-pdf.com


8T73S1802 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 8T73S1802
Beschreibung 1:2 Clock Fanout Buffer and Frequency Divider
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 24 Seiten
8T73S1802 Datasheet, Funktion
1:2 Clock Fanout Buffer and Frequency Divider 8T73S1802
DATA SHEET
General Description
Features
The 8T73S1802 is a fully integrated clock fanout buffer and frequency
divider. The input signal is frequency-divided and then fanned out to
one differential LVPECL and one LVCMOS output. Each of the
outputs can select its individual divider value from the range of ÷1,
÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level
logic) are available to select the frequency dividers and the output
enable/disable state. The single-ended LVCMOS output is
phase-delayed by 650ps to minimize coupling of LVCMOS switching
into the differential output during its signal transition.
The 8T73S1802 is optimized to deliver very low phase noise clocks.
The VBB output generates a common-mode voltage reference for the
differential clock input so that connecting the VBB pin to an unused
input (nCLK) enables to use of single-ended input signals. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The
device is a member of the high-performance clock family from IDT.
• High-performance fanout buffer clock and fanout buffer
• Input clock signal is distributed to one LVPECL and one LVCMOS
output
• Configurable output dividers for both LVPECL and LVCMOS
outputs
• Supports clock frequencies up to 1000MHz (LVPECL) and up to
200MHz (LVCMOS)
• Flexible differential input supports LVPECL, LVDS and CML
• VBB generator output supports single-ended input signal
applications
• Optimized for low phase noise
• 650ps delay between LVCMOS and LVPECL minimizes coupling
between outputs
• Supply voltage: 3.3V or 2.5V
• -40°C to 85°C ambient operating temperature
• 16 VFQFN package (3mm x 3mm)
8T73S1802 REVISION 1 08/31/15
1 ©2015 Integrated Device Technology, Inc.






8T73S1802 Datasheet, Funktion
8T73S1802 DATA SHEET
Table 4B. 2.5V Power Supply Characteristics, VCC = VCCO_QA = VCCO_QB = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC Power Supply Voltage
2.375 2.5 2.625
VCCO_QA,
VCCO_QB
Output Supply Voltage
2.375 2.5 2.625
All outputs enabled and terminated with
50to VCC – 2V on LVPECL outputs and
10pF on LVCMOS output;
114
ICC
Power Supply Current1
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, VCC = 2.5V
Outputs enabled, no load;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, VCC = 2.625V
96
ICCZ
Power Supply Current1
Outputs Disabled, EN = 0,
fIN = 0Hz, VCC = 2.625V
1.5
All outputs enabled and terminated with
50to VCC – 2V on LVPECL outputs and
IEE Power Supply Current
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS
85 99
NOTE 1. ICC includes output current.
Units
V
V
mA
mA
mA
mA
Table 4C. Differential Characteristics, VCC = VCCO_QA = 3.0V to 3.465V or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
IIH
Input High Current CLK, nCLK
VCC = VIN = VCC_MAX
65
IIL Input Low Current CLK, nCLK VCC = VCC_MAX, VIN = 0V
-10
RIN Input Impedance CLK, nCLK
22
VBB Reference Voltage for Input Bias
VOH Output High Voltage1
VOL Output Low Voltage1
IBB = -0.2mA
VCC – 1.4
VCCO_QA – 1.18
VCCO_QA – 1.98
VCC – 1.2
VCCO_QA – 0.81
VCCO_QA – 1.55
IOZH
Output Disabled Leakage Current2
VCC = VCCO_QA_MAX
VO = VCC-0.8V
40
IOZL
Output Disabled Leakage Current2
VCC = VCCO_QA_MAX
VO = 0V
5
NOTE 1. QA, nQA Outputs terminated with 50to VCC – 2V.
NOTE 2. Maximum voltage applied to a disabled (high-impedance) output is 3.465V.
Units
µA
µA
k
V
V
V
µA
µA
1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
6
REVISION 1 08/31/15

6 Page









8T73S1802 pdf, datenblatt
8T73S1802 DATA SHEET
Parameter Measurement Information
2V
VCC,
VCCO_QA
SCOPE
Qx
nQx
VEE
-1.0V to -1.465V
3.3 Core/3.3V LVPECL Output Load AC Test Circuit
1.5V to 1.7325V
VCC,
VCCO_QB
VEE
-1.5V to -1.7325V
SCOPE
Qx
3.3 Core/3.3V LVCMOS Output Load AC Test Circuit
2V
VCC,
VCCO_QA
SCOPE
Qx
nQx
VEE
-0.5V ± 0.125V
2.5V Core/2.5V LVPECL Output Load AC Test Circuit
1.25V±5%
VCC,
VCCO_QB
VEE
-1.25V±5%
SCOPE
Qx
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
VCC
nCLK
CLK
V
PP
VEE
Cross Points
V
CMR
Differential Input Level
1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
VO(pp)
VDIFF_OUT
Differential Voltage Swing = 2 x Single-ended VO(pp)
Single-Ended & Differential Output Voltage Swing
12 REVISION 1 08/31/15

12 Page





SeitenGesamt 24 Seiten
PDF Download[ 8T73S1802 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8T73S18021:2 Clock Fanout Buffer and Frequency DividerIntegrated Device Technology
Integrated Device Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche