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CLC2023 Schematic ( PDF Datasheet ) - Exar

Teilenummer CLC2023
Beschreibung RRIO Amplifier
Hersteller Exar
Logo Exar Logo 




Gesamt 18 Seiten
CLC2023 Datasheet, Funktion
CLC2023
Dual, Low Distortion, Low Offset, RRIO Amplifier
General Description
The CLC2023 is a dual channel, high-performance, voltage feedback
amplifier with low input voltage noise and ultra low distortion. The CLC2023
offers 6mV maximum input offset voltage, 3.5nV/√Hz broadband input
voltage noise, and 0.00005% THD at 1kHz. It also provides 55MHz gain
bandwidth product and 12V/μs slew rate making them well suited for
applications requiring precision DC performance and high AC performance.
This high-performance amplifier also offers a rail-to-rail input and output,
simplifying single supply designs and offering larger dynamic range
possibilities. The input range extends beyond the rails by 300mV.
The CLC2023 is designed to operate from 2.5V to 12V supplies and
operate over the extended temperature range of -40°C to +125°.
F E AT U R E S
■■ 6mV maximum input offset voltage
■■ 0.00005% THD at 1kHz
■■ 5.3nV/√Hz input voltage noise > 10kHz
■■ -90dB/-85dB HD2/HD3 at 100kHz, RL = 100Ω
■■ <-100dB HD2 and HD3 at 10kHz, RL = 1kΩ
■■ Rail-to-rail input and output
■■ 55MHz unity gain bandwidth
■■ 12V/μs slew rate
■■ -40°C to +125°C operating temperature
range
■■ Fully specified at 3 and ±5V supplies
■■ CLC2023: ROHS compliant MSOP-8,
SOIC-8 package options
A P P L I C AT I O N S
■■ Active filters
■■ Sensor interface
■■ HIgh-speed transducer amp
■■ Medical instrumentation
■■ Probe equipment
■■ Test equipment
■■ Smoke detectors
■■ Hand-held analytic instruments
■■ Current sense applications
Ordering Information - back page
Typical Application
+2.7
6.8μF
+
In
RIN
0.1μF
+½
CLC2023
-
Rf Rg
Out
ROUT
Crosstalk vs. Frequency
-60
-65
-70
-75
-80
-85
-90
-95
-100
0.01
Vs = +/- 5V, RL = 150, VOUT = 2Vpp
0.1
Frequency (MHz)
1
© 2007-2014 Exar Corporation
1 / 18
exar.com/CLC2023
Rev 1D






CLC2023 Datasheet, Funktion
CLC2023
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
Non-Inverting Frequency Response
Inverting Frequency Response
3
G=1
Rf = 0
0
G=2
-3 G = 5
G = 10
-6
1
0
-1
G = -1
-2 G = -2
-3 G = -5
G = -10
-4
-5
VOUT = 0.05Vpp
-9
0.1
1 10
Frequency (MHz)
100
-6
VOUT = 0.05Vpp
-7
0.1
1 10
Frequency (MHz)
100
Frequency Response vs. CL Frequency Response vs. CL without RS
1
0
-1 CL = 500pF
Rs = 10Ω
-2
CL = 1000pF
-3 Rs = 7.5Ω
-4 CL = 3000pF
Rs = 4Ω
-5
-6
-7
0.1
VOUT = 0.05Vpp
1 10
Frequency (MHz)
100
4
2
CL = 500pF
0
-2
-4
-6
-8
0.1
VOUT = 0.05Vpp
Rs = 0Ω
CL = 300pF
CL = 100pF
CL = 50pF
CL = 10pF
1 10
Frequency (MHz)
100
Frequency Response vs. VOUT
Frequency Response vs. RL
3
0
VOUT = 1Vpp
-3 VOUT = 2Vpp
VOUT = 4Vpp
-6
-9
0.1
1 10
Frequency (MHz)
100
2
1
0
-1
-2
-3
-4
-5 VOUT = 0.05Vpp
-6
0.1
RL = 2.5KΩ
RL = 1KΩ
RL = 50Ω
RL = 150Ω
1 10
Frequency (MHz)
100
© 2007-2014 Exar Corporation
6 / 18
exar.com/CLC2023
Rev 1D

6 Page









CLC2023 pdf, datenblatt
CLC2023
Application Information
Basic Information
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Where TAmbient is the temperature of the working
environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
PD = Psupply - Pload
+Vs
6.8μF
Supply power is calculated by the standard power equation.
Input
+ 0.1μF
-
0.1μF
Rf
Output
RL
Rg 6.8μF
-Vs
G = 1 + (Rf/Rg)
Figure 1: Typical Non-Inverting Gain Circuit
Psupply = Vsupply × IRMSsupply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((Vload)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include the
effect of the feedback network. For instance,
+Vs
6.8μF
Input
R1 +
Rg -
0.1μF
0.1μF
Rf
Output
RL
6.8μF
-Vs
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Figure 2: Typical Inverting Gain Circuit
Rloadeff in Figure 2 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - Pload
Quiescent power can be derived from the specified IS values
along with known supply voltage, Vsupply. Load power can
be calculated as above with the desired signal amplitudes
using:
(Vload)RMS = Vpeak / √2
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 500Ω load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value ThetaJA
(θJA) is used along with the total die power dissipation.
TJunction = TAmbient + (θJA × PD)
( Iload)RMS = ( Vload)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDynamic = (VS+ - Vload)RMS × ( Iload)RMS
Assuming the load is referenced in the middle of the power
rails or Vsupply/2.
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the packages
available.
© 2007-2014 Exar Corporation
12 / 18
exar.com/CLC2023
Rev 1D

12 Page





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