PDF AD5348 Data sheet ( Hoja de datos )

Número de pieza	AD5348
Descripción	Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs AD5346/AD5347/AD5348 FEATURES GENERAL DESCRIPTION AD5346: octal 8-bit DAC The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit AD5347: octal 10-bit DAC DACs, operating from a 2.5 V to 5.5 V supply. These devices AD5348: octal 12-bit DAC incorporate an on-chip output buffer that can drive the output Low power operation: 1.4 mA (max) at 3.6 V to both supply rails, and also allow a choice of buffered or Power-down to 120 nA at 3 V, 400 nA at 5 V unbuffered reference input. Guaranteed monotonic by design over all codes Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility The AD5346/AD5347/AD5348 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port. Readback The GAIN pin on these devices allows the output range to be Buffered/unbuffered reference inputs set at 0 V to VREF or 0 V to 2 × VREF. 20 ns WR time 38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging Temperature range: –40°C to +105°C APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Input data to the DACs is double-buffered, allowing simultane- ous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. All three parts are pin compatible, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. Industrial process control FUNCTIONAL BLOCK DIAGRAM VDD AGND DGND VREFAB VREFCD BUF GAIN DB1... 1 DB0 CS RD WR A2 A1 A0 CLR LDAC INTER- FACE LOGIC AD5348 INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER STRING DAC A STRING DAC B STRING DAC C STRING DAC D STRING DAC E STRING DAC F STRING DAC G STRING DAC H POWER-ON RESET BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER BUFFER VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH POWER-DOWN LOGIC 1 Protected by U.S. Patent No. 5,969,657. VREFGH Figure 1. VREFEF PD Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD5346/AD5347/AD5348 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 2. Parameter2 Output Voltage Settling Time AD5346 AD5347 AD5348 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion B Version1 Min Typ Max Unit Test Conditions/Comments VREF = 2 V 68 μs 1/4 scale to 3/4 scale change (40 H to C0 H) 79 μs 1/4 scale to 3/4 scale change (100 H to 300 H) 8 10 μs 1/4 scale to 3/4 scale change (400 H to C00 H) 0.7 V/μs 8 nV-s 1 LSB change around major carry 0.5 nV-s 1 nV-s 1 nV-s 3.5 nV-s 200 kHz VREF = 2 V ±0.1 V p-p; unbuffered mode –70 dB VREF = 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode 1 Temperature range: B Version: −40°C to +105°C; typical speciﬁcations are at 25°C. 2 See the Terminology section. 200A IOL TO OUTPUT PIN CL 50pF VOH(min) + VOL(max) 2 200A IOH Figure 2. Load Circuit for Digital Output Timing Specifications TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. Table 3. Parameter Data Write Mode (Figure 3) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Limit at TMIN, TMAX 0 0 20 5 4.5 5 5 4.5 5 4.5 20 10 20 20 0 Unit Test Condition/Comments ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min CS to WR setup time CS to WR hold time WR pulse width Data, GAIN, BUF setup time Data, GAIN, BUF hold time Synchronous mode. WR falling to LDAC falling. Synchronous mode. LDAC falling to WR rising. Synchronous mode. WR rising to LDAC rising. Asynchronous mode. LDAC rising to WR rising. Asynchronous mode. WR rising to LDAC falling. LDAC pulse width CLR pulse width Time between WR cycles A0, A1, A2 setup time A0, A1, A2 hold time Rev. A \| Page 5 of 24 5 Page Data Sheet TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 14, Figure 15, and Figure 16. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in Figure 17, Figure 18, and Figure 19. Gain Error This is a measure of the span error of the DAC, including any error in the gain of the buffer amplifier. It is the deviation in slope of the actual DAC transfer characteristic from the ideal and is expressed as a percentage of the full-scale range. This is illustrated in Figure 11. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage still positive at zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code there is a dead band over which the output voltage does not change. This is illustrated in Figure 13. ACTUAL POSITIVE GAIN ERROR NEGATIVE GAIN ERROR OUTPUT VOLTAGE IDEAL DAC CODE Figure 11. Gain Error AD5346/AD5347/AD5348 OUTPUT VOLTAGE ACTUAL GAIN ERROR AND OFFSET ERROR IDEAL POSITIVE OFFSET DAC CODE Figure 12. Positive Offset Error and Gain Error OUTPUT VOLTAGE IDEAL GAIN ERROR AND OFFSET ERROR ACTUAL NEGATIVE OFFSET DAC CODE AMPLIFIER FOOTROOM (~1mV) DEADBAND CODES NEGATIVE OFFSET Figure 13. Negative Offset Error and Gain Error Rev. A \| Page 11 of 24 11 Page

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