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Teilenummer | AD5354 |
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Beschreibung | Low Power 20bit | |
Hersteller | AKM | |
Logo | ||
Gesamt 19 Seiten ASAHI KASEI
[AK5354]
AK5354
Low Power 20bit ∆Σ ADC with PGA
FEATURES
The AK5354 is a low voltage 20bit A/D converter for digital audio system. The AK5354 also includes
Analog input PGA, therefore is suitable for microphone application and etc. As digital power supply of the
AK5354 corresponds to 1.8V, the interface with microprocessor can operate at low voltage. Analog signal
input of the AK5354 is single-ended, therefore, any external filters are not required. As the package is
16pin TSSOP, the AK5354 is a suitable for minimizing system.
FEATURES
1. Resolution : 20bits
2. Recording Functions
• 2-Stereo Inputs Selector
• Analog Input PGA
• Monaural Mixing
• Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
3. ADC Characteristics
• Input Level : 1.5Vpp@VA=2.5V (= 0.6 x VA)
• S/(N+D) : 84dB
• DR, S/N : 89dB
4. 3-wire Serial Control I/F
5. Master Clock : 256fs/384fs
6. Audio Data Format : MSB First, 2’s compliment
• 20bit MSB justified or I2S
8. Power Supply
• VA : 2.1 ∼ 3.3V (typ. 2.5V)
• VD : 1.8 ∼ 3.3V (typ. 2.5V)
9. Power Supply Current
• IPGA + ADC : 7mA
10. Ta = -40 ∼ 85°C
11. Package : 16pin TSSOP
LIN1
LIN2
RIN1
RIN2
VCOM
VA
VSS
IPGA
ADC
HPF
Audio I/F
Controller
Control Register I/F
Clock Divider
LRCK
BCLK
SDTO
VD
PDN
CSN CCLK CDTI
MCLK
MS0054-E-02
-1-
2004/12
ASAHI KASEI
[AK5354]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V; CL=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK) 256fs: Frequency
Pulse Width Low
Pulse Width High
384fs:
Frequency
Pulse Width Low
Pulse Width High
Channel Clock (LRCK) Frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
2.048
28
28
3.072
23
23
8
45
11.2896
16.9344
44.1
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
312.5
130
130
-tBLKH+50
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200(Note 7)
80
80
50
50
150(Note 7)
50(Note 7)
50
Reset / Calibration Timing
PDN Pulse Width
tPW 150
PDN “↑” to SDTO
(Note 8)
tPWV
4128
max
12.8
19.2
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note: 7. fs ≥ 19.6kHz.
In the case of fs <19.6kHz, these three parameters must meet a relationship of
(tCSW + tCSS + 7 × tCCK) > 1/(32 × fs) in addition to these specifications.
For example, When tCCK=200ns and tCSS=50ns at fs=8kHz, tCSW(min) is 2457ns. When tCSW=150ns and
tCSS=50ns fs=8kHz, tCCK(min) is 530ns.
Note: 8. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0054-E-02
-6-
2004/12
6 Page ASAHI KASEI
[AK5354]
Register Definition
Input Select
Addr
00H
Register Name
Input Select
RESET
D7 D6 D5 D4
0 0 0 HPF
0000
HPF: Select ON/OFF of the digital HPF. (0: ON, 1: OFF)
LIN2-1: Select ON/OFF of Lch input. (0: OFF, 1: ON)
RIN2-1: Select ON/OFF of Rch input. (0: OFF, 1: ON)
D3
RIN2
0
D2
RIN1
1
D1
LIN2
0
D0
LIN1
1
Mode Control 1
Addr
01H
Register Name
Mode Control 1
RESET
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 PM1 PM0
00000011
PM1-0:
Power Management (0: Power down, 1: Power up)
PM0:Power control of IPGA
PM1:Power control of ADC
When PDN pin goes “L”, all circuit in the AK5354 can be powered-down in no relation to PM1-0. When PM1-0
goes all “0”, all circuit in the AK5354 can be also powered-down. However, the contents of control registers are
held.
In case of PM1 = “1”, MCLK is not stopped.
MS0054-E-02
- 12 -
2004/12
12 Page | ||
Seiten | Gesamt 19 Seiten | |
PDF Download | [ AD5354 Schematic.PDF ] |
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