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PDF PAC1921 Data sheet ( Hoja de datos )
| Número de pieza | PAC1921 | |
| Descripción | High-Side Power/Current Monitor | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PAC1921
High-Side Power/Current Monitor with Analog Output
Features
• Configurable Measurement Type Output: Power,
Current or Bus Voltage
• Configurable Voltage Output (3V, 2V, 1.5V, 1V)
- All output values also available over SMBus
• New Device Topology
- Provides integrated average power
measurement
- Power measurements provided to
microcontroller with ADC inputs
- Unique lossless integrating architecture
allows operation at low sense voltages
- Output voltage proportional to selected
measurement
• High-Side Current Sensor
- 100 mV full-scale current sense voltage range
- Second-order delta-sigma ADC with 11-bit or
14-bit resolution
- Selectable current binary gain ranges: 1x
through 128x
• 1% Power Measurement Accuracy
• Auto-Zero Offset
• Auto Sleep State
- Automatically shifts to low-power state
(3.5 µA)
• Power Supply
- VDD = 3.3V nominal (operational range 3.0V
to 5.5V)
• Bus Range 0V to 32V
• No Input Filters Required
• Available in a 10-pin 3 mm x 3 mm VDFN RoHS
Compliant Package
Applications
• Diagnostic Equipment
• Servers
• Power Supplies
• Industrial and Power Management Systems
• Notebook and Desktop Computers
Description
The PAC1921 is a dedicated power-monitoring device
with a configurable analog output that can present
power, current or voltage. The PAC1921 is designed for
power measurement and diagnostic systems that
cannot allow for latency when performing high-speed
power management. Measurements are accumulated
in large lossless registers, allowing for integration
periods of 500 µs to 2.9 seconds. The measurement is
averaged and presented on the analog output with a
full scale range of 3V, 2V, 1.5V or 1.0V.
The PAC1921 has a READ/INT pin for host control of the
measurement integration period. This pin can be used to
synchronize readings of multiple buses between several
devices. Alternatively, PAC1921 is able to provide
outputs in a free-running mode. Information is provided
on the OUT pin and is available via SMBus if desired.
Data sampling and output attributes, such as the internal
ADC resolution (11-bit or 14-bit) and sample rate, are
configurable. The SMBus interface has more selections
for user-configurable options.
The PAC1921 is a 1% accurate power measurement
device that measures and cancels the zero offset from
the input pins. The PAC1921 was designed to monitor
power rails from 0-32V with a full-scale capability of
100 mV across the sense resistor. No input filters are
required for this device.
Package Types
PAC1921
3x3 VDFN*
VDD 1
SENSE + 2
SENSE - 3
OUT 4
GND 5
10 SM_CLK
9 SM_DATA
EP
11
8 READ/INT
7 RESERVED
6 ADDR_SEL
*Includes Exposed Thermal Pad (EP), see Table 3-1
2012-2016 Microchip Technology Inc.
DS20005293D-page 1
1 page  
PAC1921
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V,
VBUS = 0V to 32V; typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ – SENSE-) = 0V
Characteristic
Sym.
Min. Typ.
Max.
Unit
Conditions
DAC and OUT Amplifier Characteristics
Output Voltage
Swing
VOUT
Output Gain Error
Output Offset Error,
Referenced to
Output
Output Settling Time
OUTGAIN_ERR
OUTOFFSET_ ERR
tSETTLE
Output Load
Output Current Drive
OUT Short Circuit
COUT
IOUT
IOUT_SHORT
OUT Power Supply
Rejection Ratio, DC,
Referenced to Input
OUTPSRR_DC
Integration and Read Timing
Time to First
Communications
tINT_T
Update Pulse
tUPDATE
Read Pulse
tREAD
Read State Time for
Auto-Sleep State
Transition From
Sleep State to Start
of Integration Period
Transition From
Read State to Start
of Integration Period
tSLEEP
tSLEEP_TO_INT
tREAD_TO_INT
0 3.0 VDD-0.15 V 3V FSR maximum
equation in effect when VDD
falls below 3.15V
— — ±0.2 %
— ±3
±6 mV 3V FSR
——
——
——
——
— 69
42 µs Output swing from 0V to
3.0V driving up to 50 pF
50 pF
±3 mA DC
20 mA Device cannot be
damaged when OUT pin is
short circuited to GND
— dB
— 14.25
20
1.25 —
9.2
9.8 —
—
1.088 1.14
——
1.203
86
ms Time after power-up before
ready to begin
communications and
measurement
µs READ/INT pin low pulse width
range to guarantee transfer of
digital value to DAC and not
enter Read state
µs READ/INT pin minimum low
pulse width to guarantee
entry into Read state
s
µs
——
30 µs
2012-2016 Microchip Technology Inc.
DS20005293D-page 5
5 Page 
PAC1921
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PAC1921
3x3 VDFN
1
2
3
4
5
6
7
8
9
10
11
PIN DESCRIPTION
Symbol
Type
(See Table 3-2)
Function
VDD
SENSE+
SENSE–
OUT
GND
ADDR_SEL
RESERVED
READ/INT
SM_DATA
SM_CLK
EP
Power
AIO40
AIO40
AIO5
Power
AIO2
DI (5V)
DI
DIOD
DI (5V)
-
Positive Power Supply Voltage
VBUS/VSENSE+ input
VSENSE– input
Measurement Output Voltage
Ground
Selects SMBus/I2C Address
Reserved for future use. Connect to VDD for SMBus
functionality.
Controls power states
SM_DATA: SMBus/I2C Data - requires pull-up resistor
SM_CLK: SMBus/I2C Clock - requires pull-up resistor
Not internally connected, but recommend grounding.
TABLE 3-2: PIN TYPES DESCRIPTION
Pin Type
Description
Power
AIO40
AIO5
AIO2
DI
DIOD
This pin is used to power to the device.
Analog Input/Output - this pin is used as
an I/O for analog signals. Maximum volt-
age is 40V.
Analog Input Output - this pin is used as
an I/O for analog signals. Maximum volt-
age is 5V.
Analog Input/Output - this pin is used as
an I/O for analog signals. Maximum volt-
age is 2V.
Digital Input - this pin is used for digital
inputs.
Digital Input/Output Open-Drain - this pin
is used for digital I/O and is open-drain.
3.1 Positive Power Supply Voltage
(VDD)
Power supply input Voltage ranging from 3.0 to 5.5 VDC.
3.3 Measurement Output Voltage (Out)
The OUT pin provides an analog voltage based on the
upper 10 bits of the latest calculation. This pin can be
programmed for 1.0, 1.5, 2.0 and 3.0V output swings.
3.4 Ground (GND)
System ground.
3.5 SMBus/I2C Address (ADDR_SEL)
Address selection for the SMBus Slave address, based
on the pull-down resistor.
3.6 COMM_SEL
Reserved for future use, connect to VDD for SMBus
operability.
3.7 Power States (READ/INT)
This pin controls the current state of the device, either
in the INTEGRATE state, or in the READ state.
3.8 SMBus/I2C Data (SM_DATA)
3.2 VBUS/VSENSE+ Input/VSENSE– Input
(SENSE+/SENSE-)
These two pins form the differential input for measuring
voltage across a sense resistor in the application. The
positive input (Sense+) also acts as the input pin for
bus voltage.
This is the bidirectional SMBus data pin. This pin is
open-drain and requires a pull-up resistor.
3.9 SMBus/I2C Clock (SM_CLK)
This is the SMBus clock pin. This pin is open-drain and
requires a pull-up resistor.
3.10 Exposed Thermal Pad (EP)
This pad should be connected to ground for noise
immunity.
2012-2016 Microchip Technology Inc.
DS20005293D-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PAC1921.PDF ] | |
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