Datenblatt-pdf.com


CDB43L42 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer CDB43L42
Beschreibung Low Voltage/Stereo DAC With Headphone Amp
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 30 Seiten
CDB43L42 Datasheet, Funktion
CS43L42
Low Voltage, Stereo DAC with Headphone Amp
Features
Description
l 1.8 to 3.3 Volt supply
l 24-Bit conversion / 96 kHz sample rate
l 96 dB dynamic range at 3 V supply
l -85 dB THD+N
l Low power consumption
l Digital volume control
96 dB attenuation, 1 dB step size
l Digital bass and treble boost
Selectable corner frequencies
Up to 12 dB boost in 1 dB increments
l Peak signal limiting to prevent clipping
l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
l Headphone amplifier
up to 25 mWrms power output into 16 load*
25 dB analog attenuation and mute
Zero crossing click free level transitions
l ATAPI mixing functions
l 24-Pin TSSOP package
* 1 kHz sine wave at 3.3V supply
The CS43L42 is a complete stereo digital-to-analog out-
put system including interpolation, 1-bit D/A conversion,
analog filtering, volume control, line level outputs, and a
headphone amplifier, in a 24-pin TSSOP package.
The CS43L42 is based on delta-sigma modulation,
where the modulator output controls the reference volt-
age input to an ultra-linear analog low-pass filter. This
architecture allows infinite adjustment of the sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
The CS43L42 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The
CS43L42 operates from a +1.8 V to +3.3 V supply and
consumes only 16 mW of power with a 1.8 V supply with
the line amplifier powered-down. These features are
ideal for portable CD, MP3 and MD players and other
portable playback systems that require extremely low
power consumption.
ORDERING INFORMATION
CS43L42-KZ -10 to 70 °C
CDB43L42
24-pin TSSOP
Evaluation Board
RST
VA
VL
LRCK
SCLK/DEM1
SDATA
SCL/CCLK/DIF1 SDA/CDIN/DIF0 AD0/CS/DEM0
MUTEC
Control Port
External
Mute Control
Digital
Volume
Control
Bass/Treble
Boost
Limiting
∆Σ
DAC
∆Σ
DAC
Analog
Filter
Analog
Filter
VQ_HP
VA_HP
Analog
Volume
Control
Analog
Volume
Control
HP_A
HP_B
AOUTA
AOUTB
GND
MCLK
FILT+ REF_GND
VQ_LINE VA_LINE
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
APR ‘00
DS481PP1
1






CDB43L42 Datasheet, Funktion
CS43L42
ANALOG CHARACTERISTICS (Continued)
Base-rate Mode
High-Rate Mode
Parameter
Symbol Min Typ
Line Output Dynamic Performance for VA = VA_LINE = 3.0 V
Dynamic Range.
18 to 24-Bit.
16-Bit.
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
TBD
TBD
-
-
93
96
91
94
Total Harmonic Distortion + Noise.
18 to 24-Bit.
16-Bit.
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-85
-73
-33
-83
-71
-31
Interchannel Isolation.
(1 kHz)
- 100
Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V
Dynamic Range.
18 to 24-Bit.
16-Bit.
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
TBD
TBD
-
-
90
93
88
91
Total Harmonic Distortion + Noise.
18 to 24-Bit.
16-Bit.
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-76
-70
-30
-74
-68
-28
Interchannel Isolation.
(1 kHz)
- 66
Max Min Typ
- TBD 93
- TBD 96
- - 91
- - 94
TBD
-
-
-
-
-
-
-
-
-
-
-
-
-
-85
-73
-33
-83
-71
-31
100
- TBD 90
- TBD 93
- - 88
- - 91
TBD
-
-
-
-
-
-
-
-
-
-
-
-
-
-73
-70
-30
-71
-68
-28
66
Max Unit
- dB
- dB
- dB
- dB
TBD
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
- dB
- dB
- dB
- dB
TBD
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
6 DS481PP1

6 Page









CDB43L42 pdf, datenblatt
CS43L42
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE
(TA = 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
Two-Wire Mode (Note 13)
SCL Clock Frequency
fscl -
100 kHz
RST Rising Edge to Start
tirs 500
- ns
Bus Free Time Between Transmissions
tbuf 4.7
- µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
- µs
Clock Low time
tlow 4.7
- µs
Clock High Time
thigh
4.0
- µs
Setup Time for Repeated Start Condition
tsust 4.7
- µs
SDA Hold Time from SCL Falling
(Note 14) thdd
0
- µs
SDA Setup time to SCL Rising
tsud 250
- ns
Rise Time of SCL
trc -
25 ns
Fall Time SCL
tfc -
25 ns
Rise Time of SDA
trd 1 µs
Fall Time of SDA
tfd 300 ns
Setup Time for Stop Condition
tsusp
4.7
- µs
Notes: 13. The Two-Wire Mode is compatible with the I2C protocol.
14. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
S t a rt
SDA
SCL
t buf
t hdst
t high
t
low
t
hdd
R e p e a te d
S t a rt
t rd
t hdst
Stop
t fd
t fc t susp
t sud
t sust
t rc
Figure 4. Control Port Timing - Two-Wire Mode
12 DS481PP1

12 Page





SeitenGesamt 30 Seiten
PDF Download[ CDB43L42 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CDB43L42Low Voltage/Stereo DAC With Headphone AmpCirrus Logic
Cirrus Logic
CDB43L43Low Voltage/Stereo DAC With Headphone AmpCirrus Logic
Cirrus Logic

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche