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PDF ADM1033 Data sheet ( Hoja de datos )
| Número de pieza | ADM1033 | |
| Descripción | Thermal Monitor and Fan Speed (RPM) Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADM1033
Thermal Monitor and Fan
Speed (RPM) Controller
The ADM1033 is a one channel remote- and local-temperature
sensor and fan controller. The remote channel monitors the
temperature of the remote thermal diode, which may be discrete
2N3904/6s or may be located on a microprocessor die. The device also
monitors its own ambient temperature.
The ADM1033 can monitor and control the speed of cooling fan.
The user can program a target fan speed, or else use the look-up table
to input a temperature-to-fan speed profile. The look-up table can be
configured to run the fans at discrete speeds (discrete mode) or to ramp
the fan speed with temperature (linear mode).
The ADM1033 communicates over a 2-wire SMBus 2.0 interface.
An 8-level LOCATION input allows the user to choose between
SMBus 1.1 and SMBus 2.0. An ALERT output indicates error
conditions. The THERM I/O signals overtemperature as an output and
times THERM assertions as an input. Pin 8 can be configured as a
reference for the THERM (PROCHOT) input.
Features
1 Local and Remote Temperature Channels
1C Accuracy on Local and Remote Channels
Automatic Remote Temperature Channel, Up to 1 kW
Fast (Up to 64 Measurements per Second)
SMBus 2.0, 1.1, and 1.0 Compliant
SMBus Address Input/LOCATION Input to UDID
Programmable Over/Undertemperature Limits
Programmable Fault Queue
SMBusALERT Output
Fail-Safe Overtemperature Comparator Output
Fan Speed (RPM) Controller
Look-up Table for Temperature-to-Fan Speed Control
Linear and Discrete Options for Look-up Table
FAN_FAULT Output
THERM Input, Used to Time PROCHOT Assertions
REF Input, Used as Reference for THERM (PROCHOT)
3.0 V to 5.5 V Supply
Small 16-lead QSOP Package
This is a Pb-Free Device*
Applications
Desktop and Notebook PCs
Embedded Systems
Telecommunications Equipment
LCD Projectors
* For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 3
1
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QSOP−16
CASE 492
PIN ASSIGNMENT
DRIVE1 1
TACH1 2
ALERT Comp 3
NC 4
GND 5
VCC 6
THERM 7
FAN_FAULT/REF 8
ADM1033
16 SCL
15 SDA
14 ALERT
13 LOCATION
12 NC
11 NC
10 D1+
9 D1−
(Top View)
MARKING DIAGRAM
1033A
RQZ
#YYWW
1033ARQZ = Specific Device Code
# = Pb-Free Package
YY = Date Code
WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 34 of this data sheet.
Publication Order Number:
ADM1033/D
1 page  
ADM1033
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Test Conditions/Comments
Min Typ Max Unit
AGTL + INPUT (THERM)
Input High Level
− 0.75 x −
REF
V
Input Low Level
− − 0.4 V
SERIAL BUS TIMING (Note 4)
Clock Frequency, fSCLK
See Figure 2 for All Parameters
− − 400 kHz
Glitch Immunity, tSW
− 50 − ns
Bus Free Time, tBUF
1.3 −
− ms
Start Setup Time, tSU:STA
0.6 −
− ms
Start Hold Time, tHD:STA
0.6 −
− ms
Stop Condition Setup Time tSU:STO
0.6 −
− ms
SCL Low Time, tLOW
1.3 −
− ms
SCL High Time, tHIGH
0.6 −
− ms
SCL, SDA Rise Time, tr
−
−
1000
ns
SCL, SDA Fall Time, tf
− − 300 ns
Data Setup Time, tSU:DAT
100 −
− ns
Detect Clock Low Timeout, tTIMEOUT
(Note 5)
25 − 35 ms
1. Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
2. Operation at 5.5 V is guaranteed by design, not production tested.
3. Recommend use of 100 kW pullup resistors for all open-drain outputs from the ADM1033.
4. Guaranteed by design, not production tested.
5. SMBus timeout disabled by default. See the SMBus section for more information.
SCL
SDA
tBUF
PS
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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5
5 Page 
SCL
1
ADM1033
91
9
SDA
START BY
MASTER
A6
A5 A4 A3 A2 A1 A0
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W
D7
ACK. BY
ADM1033
D6 D5 D4 D3 D2 D1 D0
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADM1033
STOP BY
MASTER
Figure 18. Writing to the Address Pointer Register Only (Send Byte)
SCL
1
9
1
9
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADM1033
FRAME 2
DATA BYTE FROM ADM1033
NO ACK. BY STOP BY
ADM1033 MASTER
Figure 19. Reading Data from a Previously Selected Register
Register Addresses for Single/Block Byte Modes
The ADM1033 supports single byte as well as block read
and write operations. The register address determines
whether a single byte or multiple byte (block) operation is
run. For a single byte operation, the MSB of the register
address is set to 0; for a multiple byte operation, it is set to 1.
The number of bytes read in a multiple byte operation is set
in the #Bytes/Block Read Register at Address 0x00. The
number of bytes written to the ADM1033 is specified during
the block write operation. The addresses quoted in the
register map and throughout this data sheet assume single
byte operation. For multiple byte operations, set the MSB of
each register address to 1.
Write Operations
The SMBus specifications define protocols for read and
write operations. The ADM1033 supports send byte, write
byte, and block byte SMBus write protocols. The following
abbreviations are used in the diagrams:
S − START
P − STOP
R − READ
W − WRITE
A − ACKNOWLEDGE
A − NO ACKNOWLEDGE
Send Byte
In this operation, the master device sends a
single-command byte to a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends a 7-bit address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
S
SLAVE
ADDRESS
WA
REG
ADDRESS
A
P
Figure 20. Send Byte
The ADM1033 uses the send byte operation to write a
register address to the APR for a subsequent read from the
same address. (See Figure 24). The user may be required to
read data from the register immediately after setting up the
address. If so, the master can assert a repeat start condition
immediately after the final ACK and carry out a single byte
read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a register
address and one data byte to the slave device as follows:
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by a write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The MSB of
the register address should equal 0 for a write byte
operation. If the MSB equals 1, a block write
operation takes place.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end
the transaction.
S
SLAVE
ADDRESS
WA
REG
ADDRESS
A
DATA
AP
Figure 21. Write Byte Operation
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| PDF Descargar | [ Datasheet ADM1033.PDF ] | |
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