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DP7259 Schematic ( PDF Datasheet ) - COPAL ELECTRONICS

Teilenummer DP7259
Beschreibung Quad Digital Potentiometer
Hersteller COPAL ELECTRONICS
Logo COPAL ELECTRONICS Logo 




Gesamt 16 Seiten
DP7259 Datasheet, Funktion
Quad Digital Potentiometers
(DP) with 256 Taps and 2-wire Interface
DP7259
FEATURES
Four linear taper digital potentiometers
256 resistor taps per potentiometer
End to end resistance 50kŸ or 100kŸ
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 100Ÿ
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The DP7259 is four digital potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers
is automatically loaded into its respective wiper
control registers.
The DP7259 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40ºC to 85ºC
industrial operating temperature ranges and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
NC 1
A0 2
RW3
RH3
RL3
3
4
5
NC 6
VCC 7
RLO 8
RHO 9
RWO 10
A2 11
¯W¯P¯ 12
24 A3
23 SCL
22 RL2
21 RH2
20 RW2
19 NC
18 GND
17 RW1
16 RH1
15 RL1
14 A1
13 SDA
FUNCTIONAL DIAGRAM
SCL
SDA
WP
A0
A1
A2
A3
RH0
RH1
RH2
RH3
2-WIRE BUS
INTERFACE
WIPER CONTROL
REGISTERS
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RW0
RW1
RW2
RW3
RL0 RL1 RL2
RL3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2000 Rev. H






DP7259 Datasheet, Funktion
DP7259
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
DP7259 will be considered a slave device in all
applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The DP7259 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the DP7259 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
After the Master sends a START condition and the
slave address byte, the DP7259 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
The DP7259 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the DP7259 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the DP7259 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
WRITE OPERATIONS
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of DP7259. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The DP7259
acknowledges once more and the Master generates
the STOP condition, at which time if a non-volatile
data register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the DP7259 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the DP7259 is still
busy with the write operation, no ACK will be returned.
If the DP7259 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile data
registers. If the ¯W¯P¯ pin is tied to LOW, the data registers
are protected and become read only. Similarly, the ¯W¯P¯
pin is going low after start will interrupt non-volatile write
to data registers, while ¯W¯P¯ pin going low after an
internal write cycle has started will have no effect on any
write operation. The DP7259 will accept both slave
addresses and instructions, but the data registers are
protected from programming by the device’s failure to
send an acknowledge after data is received.
Doc. No. MD-2000 Rev. H
6 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

6 Page









DP7259 pdf, datenblatt
DP7259
INSTRUCTION FORMAT (continued)
Gang Transfer Data Register (DR) to Wiper Control Register (WCR)
S DEVICE ADDRESSES A INSTRUCTION A S
T0101 AAAAC0 0 0 1RR0 0CT
A 3210K
R
1 0 KO
P
T
Gang Transfer Wiper Control Register (WCR) to Data Register (DR)
S DEVICE ADDRESSES A INSTRUCTION A S
T0101 AAAAC1 0 0 0RR0 0CT
A 3210K
R
1 0 KO
P
T
Transfer Wiper Control Register (WCR) to Data Register (DR)
S DEVICE ADDRESSES A INSTRUCTION A S
T0101 AAAAC1 1 1 0RRPPCT
A 3210K
R
1 0 1 0 KO
P
T
Transfer Data Register (DR) to Wiper Control Register (WCR)
S DEVICE ADDRESSES A INSTRUCTION A S
T0101 AAAAC1 1 0 1RRPPCT
A 3210K
R
1 0 1 0 KO
P
T
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S DEVICE ADDRESSES A INSTRUCTION A
T0101 AAAAC0 0 1 0 0 0 PPC I I
A 3210K
R
T
10K \ \
DD
DATA
...
AS
I I CT
\ \ KO
DD P
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2000 Rev. H
12 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

12 Page





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