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PDF AS4C64M16MD1 Data sheet ( Hoja de datos )
| Número de pieza | AS4C64M16MD1 | |
| Descripción | 1 Gb (64M x 16 bit) 1.8v High Performance Mobile DDR SDRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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Revision History
AS4C64M16MD1- 60-ball FBGA PACKAGE
Revision Details
Rev 1.0 Preliminary datasheet
AS4C64M16MD1
Date
Darch 2014
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Confidential
-1- Rev.1.0 March 2014
1 page  
AS4C64M16MD1
Signal Pin Description
Pin
CLK
CLK
CKE
Type
Input
Input
CS Input
RAS, CAS Input
WE
A0 - A13 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All inputs except DQs and DMs are sampled on the rising edge
Edge of CLK.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Level
— During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge.
DQx
BA0,
BA1
LDQS,
UDQS
Input/
Output
Input
Input/
Output
UDM,
LDM
Input
VDD, VSS Supply
VDDQ
VSSQ
Supply
Level
In addition to the column address, A10 is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0,
BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
Data Input/Output pins operate in the same manner as conventional DRAMs.
Level
— Selects which bank is to be active.
Level
— Data Input/Output are synchronous edges of the DQS. LDQS for DQ0-DQ7, UDQS for
DQ8-DQ15. Active on both edges for data input/output. Center aligned to input data and
Edge aligned to output data.
Pulse
Active High In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high. If it’s high, LDM cor-
responds to DQ0-DQ7, and UDM corresponds to data on DQ8-DQ15.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Confidential
-5- Rev.1.0 March 2014
5 Page 
AS4C64M16MD1
Operation at Burst Write
During a write burst, control of the data strobe is driven by the memory controller. The LDQS, UDQS signals are centered with respect
to data and data mask. The tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the
setup and hold time parameters of data (tQDQSS & tQDQSH) and data mask (tDMDQSS & tDMDQSH). The input data is masked in the
same cycle when the corresponding LDM, UDM signal is high (i.e. the LDM,UDM mask to write latency is zero.)
LDQS, UDQS, LDM, and UDM Timing at Write
LDQS,
UDQS
LDM,
UDM
DQx
tDMDQSS
tDMDQSS
tDMDQSH
tQDQSH
tQDQSH
Q
tQDQSS
Q+1
Q+2
tQDQSS
Input Data masked
Q+3
tDMDQSH
Q+4
VIH
VTT
VIL
VIH
VTT
VIL
VIH
VTT
VIL
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal LDQS, UDQS changes
from Hi-Z to a valid logic low. This is referred to as the data strobe Write Preamble. Once the burst of write data is concluded, given no
subsequent burst write operation is initiated, the data strobe signal LDQS,UDQS transits from a valid logic low to Hi-Z. This is referred
the data strobe W rite Postamble, tWPST. For mobile DRR data is written with a delay which is defined by the parameter tDQSS,
write latency). This is different than the single data rate SDRAM where data is written in the same cycle as the Write command is issued.
DQS Pre/Postamble at Write
CLK,
/CLK
LDQS,
UDQS
WR
tDQSS
tWPREH
"Preamble"
tWPRES
tWPST
"Postamble"
VIH
VIL
VIH
VTT
VIL
DQx
Confidential
Q Q+1 Q+2 Q+3
-11-
VIH
VTT
VIL
Rev.1.0 March 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS4C64M16MD1.PDF ] | |
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