CD82C59A Datasheet PDF - Intersil Corporation
| Part Number | CD82C59A | |
| Description | CMOS Priority Interrupt Controller | |
| Manufacturers | Intersil Corporation | |
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82C59A
March 1997
CMOS Priority Interrupt Controller
Features
Description
• 12.5MHz, 8MHz and 5MHz Versions Available
- 12.5MHz Operation . . . . . . . . . . . . . . . . . . . 82C59A-12
- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A
- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the sys-
tem CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with micro-
processors such as 80C286, 80286, 80C86/88, 8086/88,
8080/85 and NSC800.
The 82C59A can handle up to eight vectored priority inter-
rupting sources and is cascadable to 64 without additional
circuitry. Individual interrupting sources can be masked or
prioritized to allow custom system configuration. Two modes
of operation make the 82C59A compatible with both 8080/85
and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
5MHz
CP82C59A-5
IP82C59A-5
CS82C59A-5
IS82C59A-5
CD82C59A-5
ID82C59A-5
MD82C59A-5/B
5962-8501601YA
MR82C59A-5/B
5962-85016013A
CM82C59A-5
PART NUMBER
8MHz
CP82C59A
IP82C59A
CS82C59A
IS82C59A
CD82C59A
ID82C59A
MD82C59A/B
5962-8501602YA
MR82C59A/B
5962-85016023A
CM82C59A
12.5MHz
CP82C59A-12
IP82C59A-12
CS82C59A-12
IS82C59A-12
CD82C59A-12
ID82C59A-12
MD82C59A-12/B
-
MR82C59A-12/B
-
CM82C59A-12
PACKAGE
28 Ld PDIP
28 Ld PLCC
CERDIP
SMD#
28 Pad CLCC
SMD#
28 Ld SOIC
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
0oC to +70oC
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 2784.2
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82C59A
Priority Resolver
This logic block determines the priorities of the bits set in the
lRR. The highest priority is selected and strobed into the cor-
responding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to
be masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.
Interrupt (INT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.
Interrupt Acknowledge (INTA)
INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (µPM) of the 82C59A.
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
Read/Write Control Logic
The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.
Chip Select (CS)
A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.
Write (WR)
A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.
Read (RD)
A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD sig-
nals to write commands into the various command registers,
as well as to read the various status registers of the chip.
This line can be tied directly to one of the system address
lines.
The Cascade Buffer/Comparator
This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CAS0 - 2) are outputs when the 82C59A is used as a mas-
ter and are inputs when the 82C59A is used as a slave. As a
master, the 82C59A sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will
send its preprogrammed subroutine address onto the Data
Bus during the next one or two consecutive INTA pulses.
(See section “Cascading the 82C59A”.)
Interrupt Sequence
The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.
These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
2. The 82C59A evaluates those requests in the priority
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
3. The CPU acknowledges the lNT and responds with an
INTA pulse.
4. Upon receiving an lNTA from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
6. These two INTA pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
The events occurring in an 80C86/88/286 system are the
same until step 4.
4. The 82C59A does not drive the data bus during the first
INTA pulse.
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
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