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CD80C88-2 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD80C88-2
Beschreibung CMOS 8/16-Bit Microprocessor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 32 Seiten
CD80C88-2 Datasheet, Funktion
80C88
March 1997
CMOS 8/16-Bit Microprocessor
[ /Title
(80C88
)
/Sub-
ject
(CMO
S 8/16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8/16
Bit uP,
micro-
proces-
sor, 8
bit, 16
bit, 8-
bit, 16-
bit,
8088,
PC)
/Cre-
ator ()
Features
Description
• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
• 1 Megabyte of Direct Memory Addressing Capability
The Intersil 80C88 high performance 8/16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, MINimum
for small systems and MAXimum for larger applications such
as multiprocessing, allow user configuration to achieve the
highest performance level.
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Intersil CMOS peripherals.
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to + 70oC
- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PACKAGE
Plastic DIP
PLCC
CERDIP
SMD#
LCC
SMD#
TEMPERATURE RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
5MHz
CP80C88
IP80C88
CS80C88
lS80C88
CD80C88
ID80C88
MD80C88/B
5962-8601601QA
MR80C88/B
5962-8601601XA
8MHz
CP80C88-2
IP80C88-2
CS80C88-2
IS80C88-2
CD80C88-2
ID80C88-2
MD80C88-2/B
-
MR80C88-2/B
-
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-1
File Number 2949.1






CD80C88-2 Datasheet, Funktion
80C88
Pin Description (Continued)
The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions
which are unique to the maximum mode are described; all other pin functions are as described above.
MAXIMUM MODE SYSTEM
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
S0 26 O STATUS: is active during clock high of T4, T1 and
S1 27 O T2, and is returned to the passive state (1, 1, 1) S2 S1 S0 CHARACTERISTICS
S2 28 O during T3 or during Tw when READY is HIGH. This 0 0 0 Interrupt Acknowledge
status is used by the 82C88 bus controller to gener-
ate all memory and I/O access control signals. Any
0
0
1 Read I/O Port
change by S2, S1 or S0 during T4 is used to 0 1 0 Write I/O Port
indicate the beginning of a bus cycle, and the return 0 1 1 Halt
to the passive state in T3 or Tw is used to indicate
the end of a bus cycle.
1 0 0 Code Access
These signals are held at a high impedance logic 1 0 1 Read Memory
one state during “grant sequence”.
1 1 0 Write Memory
1 1 1 Passive
RQ/GT0,
RQ/GT1
31
30
LOCK
29
QS1, QS0 24, 25
I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the
local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0
having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may
be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to
the 80C88 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master
(pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically
from the local bus during “grant sequence”.
3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”
request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU
then enters T4 (or T1 if no bus cycles pending).
Each master-master exchange of the local bus is a sequence of three pulses. There must be one
idle CLK cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during
T4 of the cycle when all the following conjugations are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle
apply with condition number 1 already satisfied.
O LOCK: indicates that other system bus masters are not to gain control of the system bus while
LOCK is active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains
active until the completion of the next instruction. This signal is active LOW, and is held at a high
impedance logic one state during “grant sequence”. In Max Mode, LOCK is automatically generated
during T2 of the first INTA cycle and removed during T2 of the second INTA cycle.
O QUEUE STATUS: provide status to allow external
tracking of the internal 80C88 instruction queue.
QS1 QS0 CHARACTERISTICS
The queue status is valid during the CLK cycle after
which the queue operation is performed. Note that
the queue status never goes to a high impedance
statue (floated).
0 0 No Operation
0 1 First Byte of Opcode from
Queue
1 0 Empty the Queue
1 1 Subsequent Byte from
Queue
- 34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during
a “grant sequence”.
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CD80C88-2 pdf, datenblatt
80C88
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a LOW to High transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. An high going transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves (2 bytes in the case of
word moves) of a block type instruction. Worst case
response to NMI would be for multiply, divide, and variable
shift instructions. There is no specification on the occurrence
of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure.
The signal must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
Maskable Interrupt (INTR)
The 80C88 provides a singe interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK.
To be responded to, INTR must be present (HIGH) during
the clock period preceding the end of the current instruction
or the end of a whole move for a block type instruction. INTR
may be removed anytime after the falling edge of the first
INTA signal. During interrupt response sequence, further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (INTR, NMI, software interrupt, or
single step). The FLAGS register, which is automatically
pushed onto the stack, reflects the state of the processor
prior to the interrupt. The enable bit will be zero until the old
FLAGS register is restored, unless specifically set by an
instruction.
During the response sequence (see Figure 7), the processor
executes two successive (back-to-back) interrupt acknowl-
edge cycles. The 80C88 emits to LOCK signal (maximum
mode only) from T2 of the first bus cycle until T2 of the sec-
ond. A local bus “hold” request will not be honored until the
end of the second bus cycle. In the second bus cycle, a byte
is fetched from the external interrupt system (e.g., 82C59A
PIC) which identifies the source (type) of the interrupt. This
byte is multiplied by four and used as a pointer into the inter-
rupt vector lookup table.
An INTR signal left HIGH will be continually responded to
within the limitations of the enable bit and sample period.
INTR may be removed anytime after the falling edge of the
first INTA signal. The interrupt return instruction includes a
flags pop which returns the status of the original interrupt
enable bit when it restores the flags.
ALE
T1
T2 T3 T4
T1
T2 T3
T4
LOCK
INTA
AD0-
AD7
TYPE
VECTOR
FIGURE 20. INTERRUPT ACKNOWLEDGE SEQUENCE
Halt
When a software HALT instruction is executed, the proces-
sor indicates that it is entering the HALT state in one of two
ways, depending upon which mode is strapped. In minimum
mode, the processor issues ALE, delayed by one clock
cycle, to allow the system to latch the halt status. Halt status
is available on IO/M, DT/R, and SS0. In maximum mode, the
processor issues appropriate HALT status on S2, S1 and
S0, and the 82C88 bus controller issues one ALE. The
80C88 will not leave the HALT state when a local bus hold is
entered while in HALT. In this case, the processor reissues
the HALT indicator at the end of the local bus hold. An inter-
rupt request or RESET will force the 80C88 out of the HALT
state.
Read/Modify/Write (Semaphore) Operations Via LOCK
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execu-
tion of an instruction. This allows the processor to perform
read/modify/write operations on memory (via the “exchange
register with memory” instruction), without another system
bus master receiving intervening memory cycles. This is
useful in multiprocessor system configurations to accomplish
“test and set lock” operations. The LOCK signal is activated
(LOW) in the clock cycle following decoding of the LOCK
prefix instruction. It is deactivated at the end of the last bus
cycle of the instruction following the LOCK prefix. While
LOCK is active, a request on a RQ/GT pin will be recorded,
and then honored at the end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C88 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active (LOW).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C88 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold circuits.
If interrupts are enabled, the 80C88 will recognize interrupts
and process them when it regains control of the bus.
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