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PDF ADSP-21161N Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21161N | |
| Descripción | SHARC Processor | |
| Fabricantes | Analog Devices | |
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SUMMARY
High performance 32-Bit DSP—applications in audio, medi-
cal, military, wireless communications, graphics, imaging,
motor-control, and telephony
Super Harvard Architecture—four independent buses for
dual data fetch, instruction fetch, and nonintrusive zero-
overhead I/O
Code compatible with all other sharc family DSPs
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point computation units,
each with a multiplier, ALU, shifter, and register file
Serial ports offer I2S support via 8 programmable and simul-
taneous receive or transmit pins, which support up to 16
transmit or 16 receive channels of audio
SHARC Processor
ADSP-21161N
Integrated peripherals—integrated I/O processor, 1M bit on-
chip dual-ported SRAM, SDRAM controller, glueless multi-
processing features, and I/O ports (serial, link, external
bus, SPI, and JTAG)
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit
floating-point formats
100 MHz/110 MHz core instruction rate
Single-cycle instruction execution, including SIMD opera-
tions in both computational units
Up to 660 MFLOPs peak and 440 MFLOPs sustained
performance
225-ball 17 mm 17 mm CSP_BGA package
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 u 48-BIT
DAG1
8 u 4 u 32
DAG2
8 u 4 u 32
PROGRAM
SEQUENCER
BUS
CONNECT
(PX)
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
32
32
64
64
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD IOA
64 18
MULT
DATA
REGISTER
FILE
(PEX)
16 u 40-BIT
BARREL
SHIFTER
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 u 40-BIT
MULT
JTAG TEST
AND EMULATION
GPIO
FLAGS
SDRAM
CONTROLLER
EXTERNAL PORT
ADDR BUS
MUX
6
12
8
24
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
32
HOST PORT
ALU
S
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, &
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS (4)
LINK PORTS (2)
SPI PORTS (1)
I/O PROCESSOR
5
16
20
4
Figure 1. ADSP-21161N Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Instruction Cache
The ADSP-21161N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache enables full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Hardware Circular Buffers
The ADSP-21161N’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21161N con-
tain sufficient registers to allow the creation of up to 32 circular
buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wrap-around, reduce
overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21161N can conditionally execute a multiply, an add,
and a subtract in both processing elements, while branching, all
in a single instruction.
ADSP-21161N MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21161N adds the following architectural features to
the ADSP-2116x family core.
Dual-Ported On-Chip Memory
The ADSP-21161N contains one megabit of on-chip SRAM,
organized as two blocks of 0.5M bits (Figure 3). Each block can
be configured for different combinations of code and data stor-
age. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor.
The dual-ported memory in combination with three separate
on-chip buses allow two data transfers from the core and one
from the I/O processor, in a single cycle. On the ADSP-21161N,
the memory can be configured as a maximum of 32K words of
32-bit data, 64K words of 16-bit data, 21K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to one megabit. All of the memory can be accessed as
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the amount
of data that may be stored on-chip. Conversion between the
32-bit floating-point and 16-bit floating-point formats is done
in a single instruction. While each memory block can store
combinations of code and data, accesses are most efficient when
one block stores data using the DM bus for transfers, and the
other block stores instructions and data using the PM bus for
transfers. Using the DM bus and PM bus, with one dedicated to
ADSP-21161N
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
Off-Chip Memory and Peripherals Interface
The ADSP-21161N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 62.7-M word
off-chip address space (254.7-M word if all SDRAM) is included
in the ADSP-21161N’s unified address space. The separate on-
chip buses—for PM addresses, PM data, DM addresses, DM
data, I/O addresses, and I/O data—are multiplexed at the exter-
nal port to create an external system bus with a single 24-bit
address bus and a single 32-bit data bus. Every access to external
memory is based on an address that fetches a 32-bit word.
When fetching an instruction from external memory, two 32-bit
data locations are being accessed for packed instructions.
Unused link port lines can also be used as additional data lines
DATA15–DATA0, allowing single-cycle execution of instruc-
tions from external memory, at up to 110 MHz. Figure 4 shows
the alignment of various accesses to external memory.
The external port supports asynchronous, synchronous, and
synchronous burst accesses. Synchronous burst SRAM can be
interfaced gluelessly. The ADSP-21161N also can interface glue-
lessly to SDRAM. Addressing of external memory devices is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. The ADSP-21161N pro-
vides programmable memory wait states and external memory
acknowledge controls to allow interfacing to memory and
peripherals with variable access, hold, and disable time
requirements.
SDRAM Interface
The SDRAM interface enables the ADSP-21161N to transfer
data to and from synchronous DRAM (SDRAM) at the core
clock frequency or at one-half the core clock frequency. The
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to 440M
bytes/s for 32-bit transfers and up to 660M bytes/s for 48-bit
transfers.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16Mb, 64Mb, 128Mb, and 256Mb— and
includes options to support additional buffers between the
ADSP-21161N and SDRAM. The SDRAM interface is
extremely flexible and provides capability for connecting
SDRAMs to any one of the ADSP-21161N’s four external mem-
ory banks, with up to all four banks mapped to SDRAM.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21161N supports pipelining of the address and con-
trol signals to enable such buffering between itself and multiple
SDRAM devices.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21161N
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
Rev. C | Page 5 of 60 | January 2013
5 Page 
ADSP-21161N
PIN FUNCTION DESCRIPTIONS
ADSP-21161N pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
VDDEXT or GND, except for the following:
• ADDR23–0, DATA47–0, BRST, CLKOUT (Note: These
pins have a logic-level hold circuit enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)
(Note: These pins have a pull-up enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See
Link Port Buffer Control Register Bit definitions in the
ADSP-21161N SHARC DSP Hardware Reference.)
• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,
TMS,TRST, TDI (Note: These pins have a pull-up.)
The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State (when SBTS is
asserted or when the ADSP-21161N is a bus slave).
Unlike previous SHARC processors, the ADSP-21161N con-
tains internal series resistance equivalent to 50 on all
input/output drivers except the CLKIN and XTAL pins.
Therefore, for traces longer than six inches, external series resis-
tors on control, data, clock, or frame sync pins are not required
to dampen reflections from transmission line effects for point-
to-point connections. However, for more complex networks
such as a star configuration, series termination is still
recommended.
Table 2. Pin Function Descriptions
Pin
ADDR23–0
DATA47–16
MS3–0
RD
WR
Type
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
Function
External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other
ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that
is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or
multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins
maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with
ID2–0 = 00x.
External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up
resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the
input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x.
Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if the link ports are
disabled and will not be used. In addition, DATA7–0 pins (multiplexed with L0DAT7–0) can also be used to extend
the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM
(system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half
the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0=0x1)
to enable this full instruction Width/No-packing Mode of operation.
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank sizes are fixed to 16 M words for non-SDRAM and 64M words for SDRAM.
The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the
other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a
multiprocessor system, the MSx signals are tracked by slave SHARCs.
Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from
the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD
for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven
by the bus master. RD has a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP
registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers.
In a multiprocessing system, the bus master drives WR. WR has a 20 k internal pull-up resistor that is enabled
for DSPs with ID2–0=00x.
Rev. C | Page 11 of 60 | January 2013
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-21161N.PDF ] | |
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