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PDF AD7898 Data sheet ( Hoja de datos )
| Número de pieza | AD7898 | |
| Descripción | Serial 220 kSPS ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Fast 12-Bit ADC with 220 kSPS Throughput Rate
8-Lead SOIC
Single 5 V Supply Operation
High Speed, Flexible, Serial Interface that
Allows Interfacing to 3 V Processors
On-Chip Track/Hold Amplifier
Selection of Input Ranges
؎10 V for AD7898-10
؎2.5 V for AD7898-3
High Input Impedance
Low Power: 22.5 mW Max
5 V, 12-Bit, Serial 220 kSPS
ADC in an 8-Lead Package
AD7898*
FUNCTIONAL BLOCK DIAGRAM
AD7898
REF IN
VDD
TRACK/HOLD
VIN
SIGNAL
SCALING*
12-BIT
ADC
CONVST
OUTPUT
REGISTER
GND VDRIVE
*AD7898-10, AD7898-3
SCLK SDATA
GENERAL DESCRIPTION
The AD7898 is a fast 12-bit ADC that operates from a single
5 V supply and is housed in a small 8-lead SOIC package. The
part contains a successive approximation A/D converter, an on-
chip track/hold amplifier, an on-chip clock, and a high speed
serial interface.
The AD7898 offers two modes of operation. In Mode 0, con-
version is initiated by the CONVST input and the conversion
process is controlled by an internal clock oscillator. In this mode,
the serial interface consists of three wires and the AD7898 is
capable of throughput rates up to 220 kSPS. In Mode 1, the
conversion process is controlled by an externally applied SCLK
with data being accessed from the part during conversion. In
this mode, the serial interface consists of three wires and the
AD7898 is capable of throughput rates up to 220 kSPS.
In addition to the traditional dc accuracy specifications, such as
linearity and full-scale and offset errors, the AD7898 is specified
for dynamic performance parameters, including harmonic dis-
tortion and signal-to-noise ratio.
The part accepts an analog input range of ± 10 V (AD7898-10)
and ± 2.5 V (AD7898-3), and operates from a single 5 V supply,
consuming only 22.5 mW max.
The part is available in an 8-lead Standard Small Outline
Package (SOIC).
PRODUCT HIGHLIGHTS
1. Fast, 12-Bit ADC in 8-Lead Package
The AD7898 contains a 220 kSPS ADC, a track/hold ampli-
fier, control logic, and a high speed serial interface, all in an
8-lead package. This offers considerable space saving over
alternative solutions.
2. Low Power, Single-Supply Operation
The AD7898 operates from a single 5 V supply and con-
sumes only 22.5 mW. The VDRIVE function allows the serial
interface to connect directly to either 3 V or 5 V processor
systems independent of VDD.
3. Flexible, High Speed Serial Interface
The part provides a flexible, high speed serial interface that
has two distinct modes of operation. Mode 0 provides a three-
wire interface with data being accessed from the AD7898
when conversion is complete. Mode 1 offers a three-wire
interface with data being accessed during conversion.
4. Power-Down Mode
The AD7898 offers a proprietary power-down capability
when operated in Mode 1, making the part ideal for portable
or hand-held applications.
*Protected by U.S. Patent No. 6,681,332
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD7898
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION
REF IN 1
8 VDD
VIN 2 AD7898 7 CS / CONVST
TOP VIEW
GND 3 (Not to Scale) 6 VDRIVE
SCLK 4
5 SDATA
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Model
Temperature Range Linearity Error1
SNR
Package Option2
AD7898AR-10
AD7898AR-10REEL
AD7898AR-10REEL7
AD7898ARZ-103
AD7898ARZ-10REEL3
AD7898ARZ-10REEL73
AD7898AR-3
AD7898AR-3REEL
AD7898AR-3REEL7
EVAL-AD7898CB
EVAL-CONTROL BRD24
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
71 dB
71 dB
71 dB
71 dB
71 dB
71 dB
71 dB
71 dB
71 dB
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
NOTES
1Linearity Error refers to integral linearity error.
2R = SOIC.
3Z = Pb-Free part.
4This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7898 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD pre-
cautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
5 Page 
AD7898
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7898.
The GND pin is connected to the analog ground plane of the
system. REF IN is connected to a decoupled 2.5 V supply from
a reference source, the AD780. This provides the analog refer-
ence for the part. The AD7898 is connected to a VDD of 5 V,
the serial interface is connected to a 3 V microprocessor. The
VDRIVE pin of the AD7898 is connected to the same 3 V supply
as the microprocessor to allow a 3 V logic interface. The conver-
sion result from the AD7898 is output in a 16-bit word with
four leading zeros followed by the MSB of the 12-bit result. For
applications where power consumption is of concern, the power-
down mode should be used between conversions or bursts of
several conversions to improve power performance. See Modes
of Operation section.
10F
5V
SUPPLY
0.1F
SERIAL
INTERFACE
VDD
؎2.5V OR
؎10V
INPUT
VIN
GND
SCLK
AD7898
SDATA
CS/CONVST
REF IN
VDRIVE
0.1F
2.5V
AD780
C/P
10F
0.1F
3V
SUPPLY
Figure 5. Typical Connection Diagram
VDRIVE Feature
The AD7898 has the VDRIVE feature. VDRIVE controls the voltage
at which the Serial Interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the AD7898 were operated with a VDD of 5 V, and the VDRIVE
pin could be powered from a 3 V supply. The AD7898 has good
dynamic performance with a VDD of 5 V while still being able to
interface to 3 V digital parts. Care should be taken to ensure
VDRIVE does not exceed VDD by more than 0.3 V (see Absolute
Maximum Ratings section).
Track/Hold Section
The track/hold amplifier on the analog input of the AD7898
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
track/hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
220 kSPS (i.e., the track/hold can handle input frequencies in
excess of 112 kHz). The track/hold amplifier acquires an input
signal to 12-bit accuracy in less than 0.5 µs.
The operation of the track/hold is essentially transparent to the
user. When in operating Mode 0, the track/hold amplifier goes
from its tracking mode to its hold mode at the start of conversion
(i.e., the falling edge of CONVST). The aperture time for the
track/hold (i.e., the delay time between the external CONVST
signal and the track/hold actually going into hold) is typically
15 ns. At the end of conversion (after 3.3 µs max), the part
returns to its tracking mode. The acquisition time of the track/
hold amplifier begins at this point.
When in operating in Mode 1, the falling edge of CS will put
track-and-hold into hold mode. On the 14th SCLK falling edge
after the falling edge of CS, the track-and-hold will go back into
track (see Serial Interface section). The acquisition time of the
track/hold amplifier begins at this point.
Reference Input
The reference input to the AD7898 is buffered on-chip with a
maximum reference input current of 1 µA. The part is specified
with a 2.5 V reference input voltage. Errors in the reference
source will result in gain errors in the AD7898’s transfer func-
tion and will add to the specified full-scale errors on the part.
Suitable reference sources for the AD7898 include the AD780
and AD680 precision 2.5 V references.
SERIAL INTERFACE
The serial interface to the AD7898 consists of just three wires: a
serial clock input (SCLK), the serial data output (SDATA) and
a CS/CONVST input depending on the mode of operation.
This allows for an easy-to-use interface to most microcontrol-
lers, DSP processors and shift registers. There is also a VDRIVE
pin that allows the serial interface to connect directly to either
3 V or 5 V processor systems independent of VDD. The serial
interface operation is different in Mode 0 and Mode 1 operation
and is determined by which mode is selected. Upon power-up,
the default mode of operation is Mode 0. To select Mode 1
operation see the Mode Selection section. The serial interface
operation in Mode 0 and Mode 1 is described in detail in the
Operating Modes section.
OPERATING MODES
Mode 0 Operation
The timing diagram in Figure 6 shows the AD7898 operating in
Mode 0 where the falling edge of CONVST starts conversion
and puts the track/hold amplifier into its hold mode. The con-
version is complete 3.3 µs max after the falling edge of CONVST,
and new data from this conversion is available in the output
register of the AD7898. A read operation accesses this data.
This read operation consists of 16 clock cycles and the length of
this read operation will depend on the serial clock frequency.
For the fastest throughput rate (with a serial clock of 15 MHz,
5 V operation) the read operation will take 1.066 µs. Once the
read operation has taken place, the required quiet time should
be allowed before the next falling edge of CONVST to optimize
the settling of the track/hold amplifier before the next conver-
sion is initiated. A serial clock of less than 15 MHz can be used,
but this will, in turn, mean that the throughput time will increase.
The read operation consists of 16 serial clock pulses to the out-
put shift register of the AD7898. After 16 serial clock pulses, the
shift register is reset, and the SDATA line is three-stated. If
there are more serial clock pulses after the 16th clock, the shift
register will be moved on past its reset state. However, the shift
register will be reset again on the falling edge of the CONVST
signal to ensure that the part returns to a known state after every
conversion cycle. As a result, a read operation from the output
register should not straddle the falling edge of CONVST as
the output shift register will be reset in the middle of the read
operation, and the data read back into the microprocessor will
appear invalid.
–10–
REV. A
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD7898.PDF ] | |
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