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AD7890 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7890
Beschreibung 12-Bit Serial Data Acquisition System
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD7890 Datasheet, Funktion
FEATURES
Fast 12-bit ADC with 5.9 μs conversion time
Eight single-ended analog input channels
Selection of input ranges:
±10 V for AD7890-10
0 V to 4.096 V for AD7890-4
0 V to 2.5 V for AD7890-2
Allows separate access to multiplexer and ADC
On-chip track/hold amplifier
On-chip reference
High-speed, flexible, serial interface
Single supply, low-power operation (50 mW maximum)
Power-down mode (75 μW typ)
GENERAL DESCRIPTION
The AD7890 is an 8-channel 12-bit data acquisition system. The
part contains an input multiplexer, an on-chip track/hold
amplifier, a high speed 12-bit ADC, a 2.5 V reference, and a
high speed, serial interface. The part operates from a single 5 V
supply and accepts an analog input range of ±10 V (AD7890-10),
0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2).
The multiplexer on the part is independently accessible. This
allows the user to insert an antialiasing filter or signal
conditioning, if required, between the multiplexer and the
ADC. This means that one antialiasing filter can be used for all
eight channels. Connection of an external capacitor allows the
user to adjust the time given to the multiplexer settling to
include any external delays in the filter or signal conditioning
circuitry.
Output data from the AD7890 is provided via a high speed
bidirectional serial interface port. The part contains an on-chip
control register, allowing control of channel selection,
conversion start, and power-down via the serial port. Versatile,
high speed logic ensures easy interfacing to serial ports on
microcontrollers and digital signal processors.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale, and offset errors, the AD7890 is also
specified for dynamic performance parameters including
harmonic distortion and signal-to-noise ratio.
LC2MOS 8-Channel, 12-Bit
Serial Data Acquisition System
AD7890
FUNCTIONAL BLOCK DIAGRAM
VDD
MUX SHA REF OUT/
OUT IN REF IN
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
SIGNAL
SCALING1
AD7890
2k2.5V
REFERENCE
MUX
12-BIT
ADC
TRACK/HOLD
CLOCK
OUTPUT/CONTROL REGISTER
CEXT
CONVST
AGND AGND DGND CLK
IN
SCLK TFS RFS DATA DATA SMODE
OUT IN
1NO SCALING ON AD7890-2
Figure 1.
Power dissipation in normal mode is low at 30 mW typical and the
part can be placed in a standby (power-down) mode if it is not
required to perform conversions. The AD7890 is fabricated in
Analog Devices, Inc.’s Linear Compatible CMOS (LC2MOS)
process, a mixed technology process that combines precision
bipolar circuits with low power CMOS logic. The part is available
in a 24-lead, 0.3" wide, plastic or ceramic dual-in-line package or in
a 24-lead small outline package (SOIC_W).
PRODUCT HIGHLIGHTS
1. Complete 12-Bit Data Acquisition System-on-a-Chip.
The AD7890 is a complete monolithic ADC combining an
8-channel multiplexer, 12-bit ADC, 2.5 V reference, and a
track/hold amplifier on a single chip.
2. Separate Access to Multiplexer and ADC.
The AD7890 provides access to the output of the
multiplexer allowing one antialiasing filter for 8 channels—
a considerable savings over the 8 antialiasing filters required if
the multiplexer is internally connected to the ADC.
3. High Speed Serial Interface.
The part provides a high speed serial interface for easy
connection to serial ports of microcontrollers and DSP
processors.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7890 Datasheet, Funktion
AD7890
TIMING SPECIFICATIONS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, fCLK IN = 2.5 MHz external, MUX OUT connected to SHA IN.
Parameter1, 2
f3
CLKIN
tCLKIN IN LO
tCLK IN HI
tr 4
tf4
tCONVERT
tCST
Self-Clocking Mode
t1
t2 5
t3
t4
t55
t6
t7 6
t8
t9
t10
t11
t12
External Clocking Mode
t13
t145
t15
t16
t175
t18
t196
t19A6
t20
t21
t22
t23
Limit at TMIN, TMAX (A, B, S Versions)
100
2.5
0.3 × tCLK IN
0 3 × tCLK IN
25
25
5.9
100
tCLK IN HI + 50
25
tCLK IN HI
tCLK IN LO
20
40
50
0
tCLK IN + 50
0
20
10
20
20
40
50
50
35
20
50
90
20
10
15
40
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
μs max
ns min
Conditions/Comments
Master Clock Frequency. For specified performance.
Master Clock Input Low Time.
Master Clock Input High Time.
Digital Output Rise Time. Typically 10 ns.
Digital Output Fall Time. Typically 10 ns.
Conversion Time.
CONVST Pulse Width.
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
RFS Low to SCLK Falling Edge.
RFS Low to Data Valid Delay.
SCLK High Pulse Width.
SCLK Low Pulse Width.
SCLK Rising Edge to Data Valid Delay.
SCLK Rising Edge to RFS Delay.
Bus Relinquish Time after Rising Edge of SCLK.
TFS Low to SCLK Falling Edge.
Data Valid to TFS Falling Edge Setup Time (A2 Address Bit).
Data Valid to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Hold Time.
TFS to SCLK Falling Edge Hold Time.
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
RFS Low to SCLK Falling Edge Setup Time.
RFS Low to Data Valid Delay.
SCLK High Pulse Width.
SCLK Low Pulse Width.
SCLK Rising Edge to Data Valid Delay.
RFS to SCLK Falling Edge Hold Time.
Bus Relinquish Time after Rising Edge of RFS.
Bus Relinquish Time after Rising Edge of SCLK.
TFS Low to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Setup Time.
Data Valid to SCLK Falling Edge Hold Time.
TFS to SCLK Falling Edge Hold Time.
1 Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2 See Figure 10 to Figure 13.
3 The AD7890 is production tested with fCLK IN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4 Specified using 10% and 90% points on waveform of interest.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
1.6mA
TO OUTPUT
PIN
50pF
2.1V
200µA
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. C | Page 5 of 28

6 Page









AD7890 pdf, datenblatt
THEORY OF OPERATION
CONVERTER DETAILS
The AD7890 is an 8-channel, 12-bit, single supply, serial data
acquisition system. It provides the user with signal scaling,
multiplexer, track/hold, reference, ADC, and versatile serial
logic functions on a single chip. The signal scaling allows the
part to handle ±10 V input signals (AD7890-10) and 0 V to
4.096 V input signals (AD7890-4) while operating from a single
5 V supply. The AD7890-2 contains no signal scaling and
accepts an analog input range of 0 V to 2.5 V. The part operates
from a 2.5 V reference, which can be provided from the part’s
own internal reference or from an external reference source.
Unlike other single chip data acquisition solutions, the AD7890
provides the user with separate access to the multiplexer and
the ADC. This means that the flexibility of separate multiplexer
and ADC solutions is not sacrificed with the one-chip solution.
With access to the multiplexer output, the user can implement
external signal conditioning between the multiplexer and the
track/hold. It means that one antialiasing filter can be used on
the output of the multiplexer to provide the antialiasing
function for all eight channels.
Conversion is initiated on the AD7890 either by pulsing the
CONVST input or by writing a Logic 1 to the CONV bit of the
control register. When using the hardware CONVST input, on
the rising edge of the CONVST signal, the on-chip track/hold
goes from track to hold mode and the conversion sequence is
started, provided the internal pulse has timed out. This internal
pulse (which appears at the CEXT pin) is initiated whenever the
multiplexer address is loaded to the AD7890 control register.
This pulse goes from high to low when a serial write to the part
is initiated. It starts to discharge on the sixth falling clock edge
of SCLK in a serial write operation to the part. The track/hold
cannot go into hold and conversion cannot be initiated until the
CEXT pin has crossed its trigger point of 2.5 V. The discharge
time of the voltage on CEXT depends upon the value of capacitor
connected to the CEXT pin (see the CEXT Functioning section).
The fact that the pulse is initiated every time a write to the
control register takes place means that the software conversion
start and track/hold signal is always delayed by the internal pulse.
The conversion clock for the part is generated from the clock
signal applied to the CLK IN pin of the part. Conversion time
for the AD7890 is 5.9 μs from the rising edge of the hardware
CONVST signal and the track/hold acquisition time is 2 μs. To
obtain optimum performance from the part, the data read
operation or control register write operation should not occur
during the conversion or during 500 ns prior to the next
conversion.
AD7890
This allows the part to operate at throughput rates up to
117 kHz in the external clocking mode and achieve data sheet
specifications. The part can operate at slightly higher
throughput rates (up to 127 kHz), again in external clocking
mode with degraded performance (see the Timing and Control
section). The throughput rate for self-clocking mode is limited
by the serial clock rate to 78 kHz.
All unused inputs should be connected to a voltage within the
nominal analog input range to avoid noise pickup. On the
AD7890-10, if any one of the input channels which are not
being converted goes more negative than −12 V, it can interfere
with the conversion on the selected channel.
CIRCUIT DESCRIPTION
The AD7890 is offered as three part types: the AD7890-10
handles a ±10 V input voltage range, the AD7890-4 handles a
0 V to 4.096 V input range, while the AD7890-2 handles a 0 V
to 2.5 V input voltage range.
AD7890-10 Analog Input
Figure 4 shows the analog input section for the AD7890-10. The
analog input range for each of the analog inputs is ±10 V into
an input resistance of typically 33 kΩ. This input is benign with
no dynamic charging currents with the resistor attenuator stage
followed by the multiplexer and, in cases where MUX OUT is
connected to SHA IN, this is followed by the high input
impedance stage of the track/hold amplifier. The designed code
transitions occur on successive integer LSB values (such as:
1 LSB, 2 LSBs, 3 LSBs...). Output coding is twos complement
binary with 1 LSB − FSR/4096 = 20 V/4096 = 4.88 mV. The
ideal input/output transfer function is shown in Table 4.
MUX OUT
REF OUT/
REF IN
2.5V
REFERENCE
2k
TO ADC
REFERENCE
CIRCUITRY
VINX
AGND
30k
7.5k
10k
2001
AD7890-10
1EQUIVALENT ON-RESISTANCE OF MULTIPLEXER
Figure 4. AD7890-10 Analog Input Structure
Rev. C | Page 11 of 28

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