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PDF AD7707 Data sheet ( Hoja de datos )
| Número de pieza | AD7707 | |
| Descripción | Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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3 V/5 V, ±10 V Input Range, 1 mW
3-Channel 16-Bit, Sigma-Delta ADC
AD7707
FEATURES
Charge balancing ADC
16 bits, no missing codes
±0.003% nonlinearity
High level (±10 V) and low level (±10 mV) input channels
True bipolar ±100 mV capability on low level input
Channels without requiring charge pumps
Programmable gain front end
Gains from 1 to 128
3-wire serial interface
SPI, QSPI™, MICROWIRE™ and DSP compatible
Schmitt trigger input on SCLK
Ability to buffer the analog input
2.7 V to 3.3 V or 4.75 V to 5.25 V operation
Power dissipation 1 mW at 3 V
Standby current 8 μA maximum
20-lead SOIC and TSSOP packages
GENERAL DESCRIPTION
The AD7707 is a complete analog front end for low frequency
measurement applications. This 3-channel device can accept
either low level input signals directly from a transducer or high
level (±10 V) signals and produce a serial digital output. It employs
a Σ-Δ conversion technique to realize up to 16 bits of no missing
codes performance. The selected input signal is applied to a
proprietary programmable gain front end based around an analog
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be pro-
grammed via an on-chip control register allowing adjustment
of the filter cutoff and output update rate.
The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to
5.25 V supply. The AD7707 features two low level pseudo differen-
tial analog input channels, one high level input channel and a
differential reference input. Input signal ranges of 0 mV to 20 mV
through 0 V to 2.5 V can be accommodated on both low level input
channels when operating with a VDD of 5 V and a reference of
2.5 V. They can also handle bipolar input signal ranges of ±20 mV
through ±2.5 V, which are referenced to the LCOM input. The
AD7707, with a 3 V supply and a 1.225 V reference, can handle
unipolar input signal ranges of 0 mV to 10 mV through 0 V to
1.225 V. Its bipolar input signal ranges are ±10 mV through ±1.225 V.
The high level input channel can accept input signal ranges of ±10 V,
±5 V, 0 V to 10 V and 0 V to 5 V. The AD7707 thus performs all
signal conditioning and conversion for a 3-channel system.
The AD7707 is ideal for use in smart, microcontroller or DSP-
based systems. It features a serial interface that can be configured
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
AIN1
AIN2
LOCOM
AIN3
VBIAS
FUNCTIONAL BLOCK DIAGRAM
DVDD AVDD REF IN(–) REF IN(+)
AD7707
MUX
30kΩ
5kΩ
BUF
PGA
A = 1 ≈ 128
CHARGE
BALANCING
A/D CONVERTER
Σ-Δ
MODULATOR
DIGITAL FILTER
5kΩ
HICOM
15kΩ
30kΩ
SERIAL INTERFACE
REGISTER BANK
MCLK IN
MCLK OUT
CLOCK
GENERATION
SCLK
CS
DIN
DOUT
AGND DGND
Figure 1.
DRDY RESET
for 3-wire operation. Gain settings, signal polarity and update
rate selection can be configured in software using the input
serial port. The part contains self-calibration and system calibra-
tion options to eliminate gain and offset errors on the part itself
or in the system.
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
20 μW typical. This part is available in a 20-lead wide body (0.3
inch) small outline (SOIC) package and a low profile 20-lead TSSOP.
PRODUCT HIGHLIGHTS
1. The AD7707 consumes less than 1 mW at 3 V supplies and
1 MHz master clock, making it ideal for use in low power
systems. Standby current is less than 8 μA.
2. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V to 10 V,
and 0 V to 5 V high level input signals to be directly accom-
modated on the analog inputs without requiring split supplies
or charge-pumps.
3. The low level input channels allow the AD7707 to accept
input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.
4. The part features excellent static performance specifications
with 16 bits, no missing codes, ±0.003% accuracy, and low
rms noise. Endpoint errors and the effects of temperature
drift are eliminated by on-chip calibration options, which
remove zero-scale and full-scale errors.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD7707
SPECIFICATIONS
AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+);
MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Low Level Input Channels (AIN1 and AIN2)
No Missing Codes
Output Noise
Integral Nonlinearity2
Unipolar Offset Error3
Unipolar Offset Drift4
Bipolar Zero Error3
Bipolar Zero Drift4
Positive Full-Scale Error3, 5
Full-Scale Drift4, 6
Gain Error3, 7
Gain Drift4, 8
Bipolar Negative Full-Scale Error2
Bipolar Negative Full-Scale Drift4
HIGH LEVEL INPUT CHANNEL (AIN3)
No Missing Codes
Output Noise
Integral Nonlinearity2
Unipolar Offset Error9
Unipolar Offset Drift
Bipolar Zero Error9
Bipolar Zero Drift
Gain Error
Gain Drift
Negative Full-Scale Error2
LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)2
AVDD = 5 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8 to 128
AVDD = 3 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8 to 128
Normal-Mode 50 Hz Rejection2
Normal-Mode 60 Hz Rejection2
Common-Mode 50 Hz Rejection2
B Version1
16
See Table 7 to
Table 10
±0.003
0.5
0.5
0.1
0.5
0.5
±0.003
1
0.6
16
See Table 11 to
Table 13
±0.003
±10
4
±10
4
1
±0.2
0.5
±0.0012
100
105
110
130
105
110
120
130
98
98
150
Unit
Bits min
% of FSR max
μV/°C typ
μV/°C typ
μV/°C typ
μV/°C typ
ppm of FSR/°C typ
% of FSR max
μV/°C typ
μV/°C typ
Bits min
% of FSR max
mV max
μV/°Ctyp
mV max
μV/°C typ
μV/°C typ
% typ
ppm of FSR/°C typ
% of FSR typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
Conditions/Comments
Guaranteed by design; filter notch < 60 Hz
Depends on filter cutoffs and selected gain
Filter notch < 60 Hz; typically ±0.0003%
For gains of 1, 2, and 4
For gains of 8, 16, 32, 64, and 128
Typically ±0.0007%
For gains of 1 to 4
For gains of 8 to 128
Guaranteed by design; filter notch < 60 Hz
Depends on filter cutoffs and selected gain
Filter notch < 60 Hz; typically ±0.0003%
Typically within ±1.5 mV
Typically within ±1.5 mV
For gains of 1, 2, and 4
For gains of 8, 16, 32, 64, and 128
Typically within ±0.05%
Specifications for AIN and REF IN,
unless otherwise noted
Low level input channels, AIN1 and AIN2
For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH
For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH
For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH
Rev. B | Page 4 of 52
5 Page 
AD7707
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK 1
20 DGND
MCLK IN 2
MCLK OUT 3
19 DVDD
18 DIN
CS 4
RESET 5
AD7707
TOP VIEW
17 DOUT
16 DRDY
AVDD 6 (Not to Scale) 15 AGND
AIN1 7
14 REF IN(–)
LOCOM 8
13 REF IN(+)
AIN2 9
12 VBIAS
AIN3 10
11 HICOM
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
1 SCLK
2 MCLK IN
3 MCLK OUT
4 CS
5 RESET
6 AVDD
7 AIN1
8 LOCOM
9 AIN2
10 AIN3
11 HICOM
12 VBIAS
13 REF IN(+)
14 REF IN(−)
15 AGND
16 DRDY
17 DOUT
Description
Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data
from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of
pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in
smaller batches of data.
Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock
frequencies in the range of 500 kHz to 5 MHz.
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock
can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user
does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the
part is not wasting unnecessary power driving capacitive loads on MCLK OUT.
Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the
AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame
synchronization signal in communicating with the AD7707.
Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and
analog modulator of the part to power-on status.
Analog Supply Voltage, 2.7 V to 5.25 V Operation.
Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM.
Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input.
Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM.
Single-Ended High Level Analog Input Channel with respect to HICOM.
Common Input for )igh -evel *nput $hannel. Analog input on AIN3 must be referenced to this input.
VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and
AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected
to 2.5 V when AVDD = 5 V and 1.225 V when AVDD = 3 V.
Reference Input. Positive input of the differential reference input to the AD7707. The reference input is
differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between
AVDD and AGND.
Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere
between AVDD and AGND provided that REF IN(+) is greater than REF IN(−).
Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data
register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has
taken place between output updates, the DRDY line returns high for 500 × tCLK IN cycles prior to the next output
update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from
the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY
is also used to indicate when the AD7707 has completed its on-chip calibration sequence.
Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift
register can contain information from the setup register, communications register, clock register, or data register,
depending on the register selection bits of the communications register.
Rev. B | Page 10 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7707.PDF ] | |
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