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AD7703 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7703
Beschreibung 20-Bit A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD7703 Datasheet, Funktion
LC2MOS
20-Bit A/D Converter
AD7703
FEATURES
Monolithic 16-Bit ADC
0.0015% Linearity Error
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or ؎2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
FUNCTIONAL BLOCK DIAGRAM
DVDD 15
AVDD 14
AVSS
7
DVSS
6
SC1
4
SC2
17
AD7703
CALIBRATION
SRAM
CALIBRATION
MICROCONTROLLER
13 CAL
AIN 9
VREF 10
AGND 8
DGND 5
20-BIT CHARGE BALANCE A/D
CONVERTER
ANALOG
MODULATOR
6-POLE GAUSSIAN
LOW-PASS
DIGITAL FILTER
12 BP/UP
11 SLEEP
CLOCK
GENERATOR
SERIAL INTERFACE
LOGIC
20 SDATA
19 SCLK
32
CLKIN CLKOUT
1
MODE
16
CS
18
DRDY
GENERAL DESCRIPTION
The AD7703 is a 20-bit ADC that uses a S-D conversion tech-
nique. The analog input is continuously sampled by an analog
modulator whose mean output duty cycle is proportional to the
input signal. The modulator output is processed by an on-chip
digital filter with a six-pole Gaussian response, which updates the
output data register with 16-bit binary words at word rates up to
4 kHz. The sampling rate, filter corner frequency, and output
word rate are set by a master clock input that may be supplied
externally, or by a crystal controlled on-chip clock oscillator.
The inherent linearity of the ADC is excellent and endpoint accu-
racy is ensured by self-calibration of zero and full scale, which
may be initiated at any time. The self-calibration scheme can
also be extended to null system offset and gain errors in the input
channel.
The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction ensures low power dissipation, and a power-
down mode reduces the idle power consumption to only 10 µW.
PRODUCT HIGHLIGHTS
1. The AD7703 offers 20-bit resolution coupled with outstanding
0.0003% accuracy.
2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.
4. Flexible synchronous/asynchronous interface allows the
AD7703 to interface directly to the serial ports of industry-
standard microcontrollers and DSP processors.
5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD7703 Datasheet, Funktion
AD7703
CS
SDATA
t10
DATA
VALID
HI-Z
Figure 4. SSC Mode Data Hold Time
CS
SDATA
t15
DATA
VALID
HI-Z
Figure 5b. SEC Mode Data Hold Time
DRDY
CS
SCLK
SDATA
t12
t11
HI-Z
t13
DB19
t14
DB18
DB1
t16
HI-Z
DB0
Figure 5a. SEC Mode Timing Diagram
CLKIN
CS
SCLK
SDATA
t7
HI-Z t8
t4
t8
HI-Z
DB19
t5
DB18
HI-Z
t9
DB1
DB0
HI-Z
Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero-scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full-scale, a point
1.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Differential Linearity Error
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSB. A differential linearity specification of ± 1 LSB or less
guarantees monotonicity.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (VREF ± 3/2 LSB).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the
Unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
(–VREF + 0.5 LSB) when operating in the Bipolar mode.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +VREF (for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages below
–VREF without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode.
Offset Calibration Range
In the system calibration modes (SC2 low), the AD7703 calibrates
its offset with respect to the AIN pin. The offset calibration range
specification defines the range of voltages, expressed as a
percentage of VREF, that the AD7703 can accept and still accurately
calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7703 can accept in the
system calibration mode and still correctly calibrate full scale.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7703 can accept
and still accurately calibrate gain. The input span is expressed
as a percentage of VREF.
REV. E
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AD7703 pdf, datenblatt
AD7703
Input Voltage, Unipolar Mode
System Calibration
Self-Calibration
>(SGAIN 1.5 LSB)
>(VREF 1.5 LSB)
SGAIN 1.5 LSB
VREF 1.5 LSB
Table V. Output Coding
Input Voltage, Bipolar Mode
Output Codes
FFFFF
Self-Calibration
>(VREF 1.5 LSB)
System Calibration
>(SGAIN 1.5 LSB)
FFFFF
FFFFE
VREF 1.5 LSB
SGAIN 1.5 LSB
(SGAIN SOFF)/2 0.5 LSB
(VREF VAGND)/2 0.5 LSB
80000
7FFFF
VAGND 0.5 LSB
SOFF 0.5 LSB
SOFF + 0.5 LSB
<(SOFF + 0.5 LSB)
VAGND + 0.5 LSB
<(VAGND + 0.5 LSB)
00001
00000
00000
VREF + 0.5 LSB
<(VREF + 0.5 LSB)
SGAIN + 2 SOFF + 0.5 LSB
<(SGAIN +2 SOFF + 0.5 LSB)
In the Bipolar mode, the system offset calibration range is
restricted to ±0.4 VREF. It should be noted that the span restric-
tions limit the amount of offset that can be calibrated. The span
range of the converter in Bipolar mode is equidistant around the
voltage used for the zero-scale point. When the zero-scale point
is calibrated, it must not cause either of the two endpoints of the
bipolar transfer function to exceed the positive or the negative
input overrange points (+VREF + 0.1) V or (VREF + 0.1) V. If
the span range is set to a minimum (0.8 VREF), the offset voltage
can move +0.4 VREF without causing the endpoints of the trans-
fer function to exceed the overrange points. Alternatively, if the
span range is set to 2VREF, the input offset cannot move more
than +0.1 V or 0.1 V before an endpoint of the transfer func-
tion exceeds the input overrange limit.
POWER-UP AND CALIBRATION
A calibration cycle must be carried out after power-up to initial-
ize the device to a consistent starting condition and correct
calibration. The CAL pin must be held high for at least four
clock cycles, after which calibration is initiated on the falling
edge of CAL and takes a maximum of 3,145,655 clock cycles
(approximately 768 ms with a 4.096 MHz clock). See Table III.
The type of calibration cycle initiated by CAL is determined by
the SC1 and SC2 inputs, in accordance with Table III.
Drift Considerations
The AD7703 uses chopper stabilization techniques to minimize
input offset drift. Charge injection in the analog switches and
leakage currents at the sampling node are the primary sources of
offset voltage drift in the converter. Figure 13 indicates the typical
offset due to temperature changes after calibration at 25°C. Drift
is relatively flat up to 75°C. Above this temperature, leakage
current becomes the main source of offset drift. Since leakage
current doubles approximately every 10°C, the offset drifts
accordingly. The value of the voltage on the sample capacitor is
updated at a rate determined by the master clock; therefore, the
amount of offset drift that occurs will be proportional to the
elapsed time between samples. Thus, to minimize offset drift at
higher temperatures, higher CLKIN rates are recommended.
Gain drift within the converter depends mainly upon the tem-
perature tracking of the internal capacitors. It is not affected by
leakage currents so it is significantly less than offset drift. The
typical gain drift of the AD7703 is less than 40 LSB over the
specified temperature range.
Measurement errors due to offset drift or gain drift can be
eliminated at any time by recalibrating the converter. Using the
system calibration mode can also minimize offset and gain errors
in the signal conditioning circuitry. Integral and differential
linearity are not significantly affected by temperature changes.
160
CLKIN = 4.096MHz
80
0
–80
–160
–240
–320
–55 –35 –15
5 25 45 65
TEMPERATURE – ؇C
85 105 125
Figure 13. Typical Bipolar Offset vs. Temperature
after Calibration at 25°C
REV. E
–11–

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