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CD74HCT393E Schematic ( PDF Datasheet ) - Harris Corporation

Teilenummer CD74HCT393E
Beschreibung High Speed CMOS Logic Dual 4 -Stage Binary Counter
Hersteller Harris Corporation
Logo Harris Corporation Logo 




Gesamt 7 Seiten
CD74HCT393E Datasheet, Funktion
Semiconductor
September 1997
CD74HC393,
CD74HCT393
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative-Edge Clocking
• TTAyp=ic2a5lofCMAX = 60 MHz at VCC = 5V, CL = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
PKG.
NO.
CD74HC393E
-55 to 125
14 Ld PDIP E14.3
CD74HCT393E
-55 to 125
14 Ld PDIP E14.3
CD74HC393M
-55 to 125
14 Ld SOIC M14.15
CD74HCT393M
-55 to 125
14 Ld SOIC M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP 1
1MR 2
1Q0 3
1Q1 4
1Q2 5
1Q3 6
GND 7
14 VCC
13 2CP
12 2MR
11 2Q0
10 2Q1
9 2Q2
8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1653.1






CD74HCT393E Datasheet, Funktion
CD74HC393, CD74HCT393
Prerequisite for Switching Specifications (Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
PARAMETER
Reset Pulse Width
SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
tW
2 80 -
- 100 - 120 -
ns
4.5 16 -
- 20 - 24 - ns
6 14 -
- 17 - 20 - ns
HCT TYPES
Maximum Clock
Frequency
fMAX
4.5 27 -
- 22 - 18 - MHz
Clock Pulse Width
Reset Recovery Time
Reset Pulse Width
tW
tREC
tW
4.5 19 -
4.5 5 -
4.5 16 -
- 24 - 29 - ns
- 5 - 5 - ns
- 20 - 24 - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay Time
(Figure 1)
Qn to Qn + 1
nCP to nQ0
tPLH,
tPHL
CL = 50pF
tPLH,
tPHL
CL =15pF
CL = 50pF
CL = 50pF
2 - - 45 - 55 - 70 ns
4.5 - - 9 - 11 - 14 ns
5 - 4 - - - - - ns
6 - - 8 - 9 - 12 ns
2
-
- 150
-
190
-
225 ns
4.5 - - 30 - 38 - 59 ns
nCP to nQ1
tPLH,
tPHL
CL =15pF
CL = 50pF
CL = 50pF
5 - 12 - - - - - ns
6 - - 26 - 33 - 50 ns
2
-
- 190
-
245
-
295 ns
4.5 - - 38 - 49 - 59 ns
6 - - 33 - 42 - 50 ns
nCP to nQ2
tPLH,
tPHL
CL = 50pF
2
-
- 240
-
300
-
360 ns
4.5 - - 48 - 60 - 72 ns
6 - - 41 - 51 - 61 ns
nCP to nQ3
tPLH,
tPHL
CL = 50pF
2
-
- 285
-
355
-
430 ns
4.5
- 57
-
71
-
86 ns
6 - - 48 - 60 - 73 ns
MR to Qn
tPLH,
tPHL
CL = 50pF
2
-
- 135
-
170
-
205 ns
4.5 - - 27 - 34 - 41 ns
Output Transition Time
(Figure 1)
CL =15pF
CL = 50pF
tTLH, tTHL CL = 50pF
5 - 11 - - - - - ns
6 - - 23 - 29 - 35 ns
2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance
CIN CL = 50pF
Power Dissipation Capacitance CPD CL =15pF
(Notes 4, 5)
- - - 10 - 10 - 10 pF
5 - 20 - - - - - pF
6

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