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Teilenummer | DA9061 |
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Beschreibung | Entry level PMIC | |
Hersteller | Dialog Semiconductor | |
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Gesamt 30 Seiten DA9061
Entry level PMIC for applications requiring up to 6 A
General description
DA9061 is a power management integrated circuit (PMIC) optimised for supplying systems with
single- and dual-core processors, I/O, DDR memory, and peripherals. It targets mobile device,
medical equipment, entry level IVI system, and FPGA based applications.
DA9061 features three buck converters providing a total current of 6 A. High efficiency is achieved
over a wide load range by using automatic Pulse Frequency Modulation (PFM) mode. All power
switches are integrated, therefore, external Schottky diodes are not required. Furthermore, low-
profile inductors can be used with DA9061. The four LDO regulators with programmable output
voltage provide up to 300 mA.
Dynamic voltage control (DVC) allows dynamic control of DA9061 supply voltages according to the
operating point of the system. It is controlled by writing directly to the registers using the I2C
compatible 2-wire interface or the GPIOs.
DA9061 features a programmable power sequencer that handles start-up and shutdown sequences.
Power mode transitions can be triggered with software control, GPIOs, or with the on-key. Several
types of on-key presses can be detected to trigger different power mode transitions.
An integrated watchdog timer monitors the system.
Five GPIOs are able to perform system functions, including: keypad supervision, application buck,
and timing-controlled external regulators/power switches or other ICs.
DA9061 is also available as an automotive AEC-Q100 Grade 3 version.
Key features
■ Input voltage 2.8 to 5.5 V
■ Programmable power mode sequencer
■ Three buck converters with dynamic voltage ■ System supply and junction temperature
control:
monitoring
□ Buck1: 0.3 to 1.57 V, 2.5 A
■ Watchdog timer
□ Buck2: 0.8 to 3.34 V, 2 A
■ Five GPIOs
□ Buck3: 0.53 to 1.8 V, 1.5 A
■ -40 to +85 °C temperature range
□ 3 MHz switching frequency (enables low ■ 40-pin QFN, 6×6 mm package, 0.5 mm pitch
profile inductors)
■ Four LDO regulators:
■ Automotive AEC-Q100 Grade 3 variant
available
□ LDO1: 0.9 to 3.6 V, 100 mA
□ LDO2, LDO3, LDO4: 0.9 to 3.6 V, 300 mA
Applications
■ Supply for single and dual core application
processors such as ARM Cortex or i.MX6
series
■ Power supply for entry-level FPGAs
■ Automotive infotainment
■ Portable industrial and medical devices
■ E-book readers
Datasheet
CFR0011-120-00 Rev 5
Revision 3.2
1 of 82
01-Mar-2016
© 2016 Dialog Semiconductor
DA9061
Entry level PMIC for applications requiring up to 6 A
1 Package information
1.1 Pin list
Table 1: DA9061 pin description
Pin Name
Type
Table 2
Paddle GND
GND
1 VLDO1
AO
2 VLDO2
AO
3 VDD_LDO2
PS
4 IREF
AO
5 VREF
AIO
6 NC
7 VSS_ANA
GND
8 NC
9 VLDO3
AO
10 VDD_LDO34
PS
11 VLDO4
AO
12 NC
13 SDA
DIO
14 SCL
DI
15 nONKEY
DI
16 nRESETREQ
DI
17 VLX_BUCK3
AO
18 VDD_BUCK3
PS
19 VDD_BUCK2
PS
20 VLX_BUCK2
AO
21 GPIO0
DIO
22 GPIO1
DIO
23 VDDIO
PS
24 VBUCK3
AI
25 VBUCK2
AI
26 VBUCK1
AI
27 NC
28 GPIO2
DIO
29 GPIO3
DIO
30 GPIO4
DIO
31 VLX_BUCK1
AO
32 VDD_BUCK1
PS
33 NC
Description
Power grounds of the bucks, digital ground
LDO1 output voltage
LDO2 output voltage
LDO2 supply
Reference current
Reference voltage
Do not use. Leave floating.
Analog ground
Do not use. Leave floating.
LDO3 output voltage
LDO3 and LDO4 supply
LDO4 output voltage
Do not use. Leave floating.
Data signal of the 2-wire interface
Clock signal of the 2-wire interface
Input for power-on key
Reset request input
Switching node of Buck3
Buck3 supply
Buck2 supply
Switching node of Buck2
General purpose I/O, WDKICK
General purpose I/O
IO supply
Voltage feedback of Buck3
Voltage feedback of Buck2
Voltage feedback of Buck1
Do not use. Leave floating.
General purpose I/O, PWR_EN
General purpose I/O
General purpose I/O, SYS_EN
Switching node of Buck1
Buck1 supply
Do not use. Leave floating.
Datasheet
CFR0011-120-00 Rev 5
Revision 3.2
6 of 82
01-Mar-2016
© 2016 Dialog Semiconductor
6 Page DA9061
Entry level PMIC for applications requiring up to 6 A
Parameter
Data valid time acknowledge
Symbol
tVD_ACK
Test conditions
Min Typ Max
0.45
Stop condition set-up time
tSU_STO
0.26
High Speed Mode
SCL clock frequency
Start condition set-up time
fSCL
tSU_STA
Requires VDDIO ≥ 1.8 V
Note 1
0
160
3400
Start condition hold time
tH_STA
160
SCL low time
tLOW
160
SCL high time
tHIGH
60
2-wire SCL and SDA rise time tR
(input requirement)
160
2-wire SCL and SDA fall time
tF
(input requirement)
160
Data set-up time
tSU_D
10
Data hold-time
tH_D
0
Stop condition set-up time
tSU_STO
160
Note 1 Minimum clock frequency is 10 kHz if TWOWIRE_TO is enabled in register CONFIG_J.
Unit
µs
µs
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.4 LDOs
4.4.1 LDO1
Unless otherwise noted, the following is valid for TA = -40 to +85 ºC.
Table 8: LDO1 electrical characteristics
Parameter
Symbol Test conditions
Input voltage
Output voltage
Output accuracy
VDD
VLDO
VDD = VSYS
Programmable in 50 mV steps
IOUT = IMAX including static
line/load regulation
Stabilisation capacitor COUT
Including voltage and
temperature coefficient
Output capacitor ESR RCOUT_ESR
Output current
Short circuit current
Dropout voltage
IOUT
ISHORT
VDROPOUT
Static line regulation
VS_LINE
Static load regulation VS_LOAD
Line transient response VTR_LINE
f > 1 MHz including wiring
parasitics
VDD ≥ 1.8 V
IOUT = IMAX
IOUT = IMAX/3 for VDD = 1.5 V
VDD = 3.0 to 5.5 V
IOUT = IMAX
IOUT = 1 mA to IMAX
VDD = 3.0 to 3.6 V
IOUT = IMAX
tr = tf = 10 µs
Min
2.8
0.9
-3%
Typ
-55%
1.0
0
100
200
100
5
5
5
Max
5.5
3.6
+3%
Unit
V
V
+35%
300
µF
mΩ
mA
mA
150 mV
20 mV
20 mV
20 mV
Datasheet
CFR0011-120-00 Rev 5
Revision 3.2
12 of 82
01-Mar-2016
© 2016 Dialog Semiconductor
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ DA9061 Schematic.PDF ] |
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