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DA14582 Schematic ( PDF Datasheet ) - Dialog Semiconductor

Teilenummer DA14582
Beschreibung Low Power Bluetooth Smart SoC
Hersteller Dialog Semiconductor
Logo Dialog Semiconductor Logo 




Gesamt 30 Seiten
DA14582 Datasheet, Funktion
DATASHEET - PRELIMINARY
MARCH 11, 2015 V2.0
DA14582
Low Power Bluetooth Smart SoC with Audio Codec
General description
16 MHz 32 bit ARM Cortex-M0 with SWD I/F
The DA14582 integrated circuit has a fully integrated
radio transceiver, baseband processor for Bluetooth®
Smart with Audio Codec.
Dedicated Link Layer Processor
AES-128 bit encryption Processor
Memories
32 kB One-Time-Programmable (OTP) memory
The DA14582 is optimized for remote control units
42 kB System SRAM
(RCU) requiring support for voice commands and
84 kB ROM
motion/gesture recognition. Its integrated analog wide
8 kB Retention SRAM
band audio codec provides native support for analog
Power management
microphones thereby reducing the total number of
Integrated Buck DC-DC converter
components of the system while its optimized package
P0, P1, P2 and P3 ports with 3.3 V tolerance
enables designs using single-layer FR1 PCBs further-
Easy decoupling of only 4 supply pins
more contributing to the reduction of the cost of the
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
system.
battery cells
The DA14582 supports a flexible memory architecture
for storing Bluetooth profiles and custom application
code, which can be updated over the air (OTA). The
qualified Bluetooth Smart protocol stack is stored in a
dedicated ROM. All software runs on the ARM® Cor-
tex®-M0 processor via a simple scheduler.
10-bit ADC for battery voltage measurement
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
The Bluetooth Smart firmware includes the L2CAP ser-
29 General purpose I/Os
vice layer protocols, Security Manager (SM), Attribute
2 UARTs with hardware flow control up to 1 MBd
Protocol (ATT), the Generic Attribute Profile (GATT)
SPI+™ interface
and the Generic Access Profile (GAP). All profiles pub-
I2C bus at 100 kHz, 400 kHz
lished by the Bluetooth SIG as well as custom profiles
3-axis capable Quadrature Decoder
are supported.
Analog interfaces
The transceiver interfaces directly to the antenna and
is fully compliant with the Bluetooth 4.1 standard.
4-channel 10-bit ADC
14 bits wide band Codec with microphone and
28 loudspeaker analog front-end
The DA14582 has dedicated hardware for the Link
Layer implementation of Bluetooth®Smart and inter-
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
face controllers for enhanced connectivity capabilities.
Single wire antenna: no RF matching or RX/TX
switching required
Features
Supply current at VBAT3V:
Complies with Bluetooth V4.1, ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan)
Processing power
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
0 dBm transmit output power
-20 dBm output power in “Near Field Mode”
-93 dBm receiver sensitivity
________________________________________________________________________________________________
System diagram
© 2015 Dialog Semiconductor
1 www.dialog-semiconductor.com






DA14582 Datasheet, Funktion
Table 2: Pin Description
PIN NAME
TYPE
Drive
(mA)
Reset
state
(Note )
DESCRIPTION
16MCLK/P0_5
DIO
4.8
OUTPUT. Buffered 16MHz output
This clock is used as reference clock for the on-chip Codec
which is enabled via a test register bit 0x500030F0[0]=1. How-
ever, when enabled the following pins also output certain clock
signals. In this case these port pins can only be used as general
purpose inputs by setting Pxy_MODE_REG[PID]=0 and
Pxy_MODE_REG[PUPD] unequal to 3:
P0_6: XTAL32K
P0_7: RC16M
P1_0: RC32K
P1_1: RC32K_low_jitter
SPI bus interface (Refer to Table 3 for the fixed SPI pin assignment during codec operation)
SPI_CLK
DO
INPUT/OUTPUT. SPI Clock. Mapped on Px ports.
SPI_DI
DI
INPUT. SPI Data input. Mapped on Px ports.
SPI_DO
DO
OUTPUT. SPI Data output. Mapped on Px ports
SPI_EN
DI/DO
INPUT/OUTPUT. SPI Clock enable. Mapped on Px ports
I2C bus interface
SDA
DIO/
DIOD
INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on
Px ports
SCL DIO/
DIOD
INPUT/OUTPUT. I2C bus Clock with open drain port. In open
drain mode, SCL is monitored to support bit stretching by a
slave. Mapped on Px ports.
UART interface
UTX
DO
OUTPUT. UART transmit data. Mapped on Px ports
URX
DI
INPUT. UART receive data. Mapped on Px ports
URTS
DO
OUTPUT. UART Request to Send. Mapped on Px ports
UCTS
DI
INPUT. UART Clear to Send. Mapped on Px ports
UTX2
DO
OUTPUT. UART 2 transmit data. Mapped on Px ports
URX2
DI
INPUT. UART 2 receive data. Mapped on Px ports
URTS2
DO
OUTPUT. UART 2 Request to Send. Mapped on Px ports
UCTS2
DI
INPUT. UART 2 Clear to Send. Mapped on Px ports
Analog interface
ADC[0]
AI
INPUT. Analog to Digital Converter input 0. Mapped on P0[0]
ADC[1]
AI
INPUT. Analog to Digital Converter input 1. Mapped on P0[1]
ADC[2]
AI
INPUT. Analog to Digital Converter input 2. Mapped on P0[2]
ADC[3]
AI
INPUT. Analog to Digital Converter input 3. Mapped on P0[3]
Codec interface
GPIO2, GPIO3
DIO
8
I-PU
INPUT/OUTPUT. Codec General Purpose I/O ports with
selectable pull up/down resistor. Supplied from VDDIO
RSTn
DI
INPUT. Codec reset signal (active low). After startup this pin
must be kept LOW for at least 1 us (while the clock is active) to
guarantee synchronous release of the reset.
VREFp
A1 - Hi-Z OUTPUT. Positive microphone reference voltage.
VREFm
A1 -
- Ground for Codec AFE reference voltages and microphone.
Must be connected to star-point of common ground.
LSRp, LSRn A1 - Hi-Z OUTPUT. Loudspeaker earpiece outputs positive and negative.
© 2015 Dialog Semiconductor
5 Preliminary - March 11, 2015 v2.0

6 Page









DA14582 pdf, datenblatt
• 7 or 10-bit combined format transfers
• Bulk transmit mode
• Default slave address of 0x055
• Interrupt or polled-mode operation
• Handles Bit and Byte waiting at both bus speeds
• Programmable SDA hold time
3.6.4 General purpose ADC
The DA14582 is equipped with a high-speed ultra low
power 10-bit general purpose Analog-to-Digital Con-
verter (GPADC). It can operate in unipolar (single
ended) mode as well as in bipolar (differential) mode.
The ADC has its own voltage regulator (LDO) of 1.2 V,
which represents the full scale reference voltage.
Features
• 10-bit dynamic ADC with 65 ns conversion time
• Maximum sampling rate 3.3 Msample/s
• Ultra low power (5 A typical supply current at
100 ksample/s)
• Single-ended as well as differential input with two
input scales
• Four single-ended or two differential external input
channels
• Battery monitoring function
• Chopper function
• Offset and zero scale adjust
• Common-mode input level adjust
3.6.5 Quadrature decoder
This block decodes the pulse trains from a rotary
encoder to provide the step and the direction of the
movement of an external device. Three axes (X, Y, Z)
are supported.
The integrated quadrature decoder can automatically
decode the signals for the X, Y and Z axes of a HID
input device, reporting step count and direction: the
channels are expected to provide a pulse train with 90
degrees phase difference; depending on whether the
reference channel is leading or lagging, the direction
can be determined.
This block can be used for waking up the chip as soon
as there is any kind of movement from the external
device connected to it.
Features
• Three 16-bit signed counters that provide the step
count and direction on each of the axes (X, Y and Z)
• Programmable system clock sampling at maximum
16 MHz.
• APB interface for control and programming
• Programmable source from P0, P1 and P2 ports
• Digital filter on the channel inputs to avoid spikes
3.6.6 Keyboard controller
The Keyboard controller can be used for debouncing
the incoming GPIO signals when implementing a key-
board scanning engine. It generates an interrupt to the
CPU (KEYBR_IRQ).
In parallel, five extra interrupt lines can be triggered by
a state change on 32 selectable GPIOs (GPIOx_IRQ).
Features
• Monitors any of the available GPIOs (Px_y) exclud-
ing GPIO2 and GPIO3.
• Generates a keyboard interrupt on key press or key
release
• Implements debouncing time from 0 upto 63 ms
• Supports five separate interrupt generation lines
from GPIO toggling
3.6.7 Input/output ports
The DA14582 has software-configurable I/O pin
assignment, organized into ports Port 0, Port1 and
Port2.
Features
• Port 0: 8 pins, Port 1: 6 pins (including SW_CLK and
SWDIO), Port 2: 10 pins, Port 3: 5 pins
• Fully programmable pin assignment
• Selectable 25 kpull-up, pull-down resistors per pin
• Pull-up voltage either VBAT3V (BUCK mode) or
VBAT1V (BOOST mode) configurable per pin
• Fixed assignment for analog pin ADC[3:0]
• Pins retain their last state when system enters the
Extended or Deep Sleep mode.
3.7 TIMERS
3.7.1 General purpose timers
The Timer block contains 2 timer modules that are soft-
ware controlled, programmable and can be used for
various tasks.
Timer 0
• 16-bit general purpose timer
• Ability to generate 2 Pulse Width Modulated signals
(PWM0 and PWM1, with common programming)
• Programmable output frequency:
© 2015 Dialog Semiconductor
11 Preliminary - March 11, 2015 v2.0

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