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PDF DA14581 Data sheet ( Hoja de datos )
| Número de pieza | DA14581 | |
| Descripción | Low Power Bluetooth Smart SoC | |
| Fabricantes | Dialog Semiconductor | |
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DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
General description
AES-128 bit encryption Processor
The DA14581 integrated circuit is an optimized version
of the DA14580, offering a reduced boot time and sup-
porting up to 8 connections. It has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
Memories
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck/Boost DCDC converter
The DA14581 supports a flexible memory architecture
P0, P1 and P2 ports with 3.3 V tolerance
for storing Bluetooth profiles and custom application
Easy decoupling of only 4 supply pins
code, which can be updated over the air (OTA). The
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
qualified Bluetooth Smart protocol stack and the HCI
battery cells
ready software are stored in a dedicated ROM. All soft-
ware runs on the ARM® Cortex®-M0 processor via a
10-bit ADC for battery voltage measurement
Digital controlled oscillators
simple scheduler.
16 MHz crystal (±20 ppm max) and RC oscillator
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
The transceiver interfaces directly to the antenna and
I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.1 standard.
3-axes capable Quadrature Decoder
The DA14581 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Features
Single wire antenna: no RF matching or RX/TX
switching required
Complies with Bluetooth V4.1, ETSI EN 300 328 and
Supply current at VBAT3V:
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
(US) and ARIB STD-T66 (Japan)
0 dBm transmit output power
Supports up to 8 Bluetooth Smart connections
-20 dBm output power in “Near Field Mode”
Fast cold boot in less than 30 ms
-93 dBm receiver sensitivity
Processing power
Packages:
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
WLCSP 34 pins, 2.436 mm x 2.436 mm
face QFN 40 pins, 5 mm x 5 mm
Dedicated Link Layer Processor
________________________________________________________________________________________________
System diagram
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.0
1 of 152
18-Dec-2015
© 2015 Dialog Semiconductor
1 page  
DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
Table 1: Pin description
PIN NAME
TYPE
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P1_0
P1_1
P1_2
P1_3
P1_4/SWCLK
P1_5/SW_DIO
DIO
DIO
DIO
DIO
DIO
DIO
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
P2_9
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P3_0 to P3_7
DIO
Debug interface
SWDIO/P1_5
DIO
Drive
(mA)
4.8
4.8
4.8
4.8
4.8
SW_CLK/
P1_4
DIO
Clocks
XTAL16Mp
AI
XTAL16Mm
AO
XTAL32kp
AI
XTAL32km
AO
Quadrature decoder
QD_CHA_X
DI
QD_CHB_X
DI
QD_CHA_Y
DI
QD_CHB_Y
DI
QD_CHA_Z
DI
QD_CHB_Z
DI
SPI bus interface
SPI_CLK
DO
SPI_DI
DI
4.8
Datasheet
CFR0011-120-00-FM Rev 5
Reset
state
(Note )
DESCRIPTION
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
NOTE: This port is only available on the QFN40 package.
Not supported.
I-PU
I-PD
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
Revision 3.0
5 of 152
18-Dec-2015
© 2015 Dialog Semiconductor
5 Page 
DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
tain fields in the OTP should be programmed
by the following: baud rate = (serial clock frequency)/
(divisor).
4.5 POWER MODES
There are four different power modes in the DA14580:
• Active mode: System is active and operates at full
speed.
• Sleep mode: No power gating has been pro-
grammed, the ARM CPU is idle, waiting for an inter-
rupt. PD_SYS is on. PD_PER and PED_RAD
depending on the programmed enabled value.
• Extended Sleep mode: All power domains are off
except for the PD_AON, the programmed PD_RRx
and the PD_SR. Since the SysRAM retains its data,
no OTP mirroring is required upon waking up the
system.
• Deep Sleep mode: All power domains are off except
for the PD_AON and the programmed PD_RRx.
This mode dissipates the minimum leakage power.
However, since the SysRAM has not retained its
data, an OTP mirror action is required upon waking
up the system.
4.6 INTERFACES
4.6.1 UARTs
The UART is compliant to the industry-standard 16550
and is used for serial communication with a peripheral,
modem (data carrier equipment, DCE) or data set.
Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and
transmitted to the destination device. Serial data is also
received by the UART and stored for the master (CPU)
to read back.
There is no DMA support on the UART block since its
contains internal FIFOs. Both UARTs support hardware
flow control signals (RTS, CTS, DTR, DSR).
Features
• 16 bytes Transmit and receive FIFOs
• Hardware flow control support (CTS/RTS)
• Shadow registers to reduce software overhead and
also include a software programmable reset
• Transmitter Holding Register Empty (THRE) inter-
rupt mode
• IrDA 1.0 SIR mode supporting low power mode.
• Functionality based on the 16550 industry standard:
• Programmable character properties, such as num-
ber of data bits per character (5-8), optional
• parity bit (with odd or even select) and number of
stop bits (1, 1.5 or 2)
• Line break generation and detection
• Prioritized interrupt identification
• Programmable serial data baud rate as calculated
4.6.2 SPI+
This interface supports a subset of the Serial Periph-
eral Interface (SPITM). The serial interface can transmit
and receive 8, 16 or 32 bits in master/slave mode and
transmit 9 bits in master mode. The SPI+ interface has
enhanced functionality with bidirectional 2x16-bit word
FIFOs.
SPI is a trademark of Motorola, Inc.
Features
• Slave and Master mode
• 8 bit, 9 bit, 16 bit or 32 bit operation
• Clock speeds upto 16 MHz for the SPI controller.
Programmable output frequencies of SPI source
clock divided by 1, 2, 4, 8
• SPI clock line speed up to 8 MHz
• SPI mode 0, 1, 2, 3 support (clock edge and phase)
• Programmable SPI_DO idle level
• Maskable Interrupt generation
• Bus load reduction by unidirectional writes-only and
reads-only modes.
Built-in RX/TX FIFOs for continuous SPI bursts.
4.6.3 I2C interface
The I2C interface is a programmable control bus that
provides support for the communications link between
Integrated Circuits in a system. It is a simple two-wire
bus with a software-defined protocol for system control,
which is used in temperature sensors and voltage level
translators to EEPROMs, general-purpose I/O, A/D
and D/A converters.
Features
• Two-wire I2C serial interface consists of a serial data
line (SDA) and a serial clock (SCL)
• Two speeds are supported:
• Standard mode (0 to 100 kbit/s)
• Fast mode (<= 400 kbit/s)
• Clock synchronization
• 32 deep transmit/receive FIFOs
• Master transmit, Master receive operation
• 7 or 10-bit addressing
• 7 or 10-bit combined format transfers
• Bulk transmit mode
• Default slave address of 0x055
• Interrupt or polled-mode operation
Datasheet
Revision 3.0
18-Dec-2015
CFR0011-120-00-FM Rev 5
11 of 152
© 2015 Dialog Semiconductor
11 Page | ||
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| PDF Descargar | [ Datasheet DA14581.PDF ] | |
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