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GS881Z36T Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS881Z36T
Beschreibung 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS881Z36T Datasheet, Funktion
Preliminary
GS881Z18/36T-11/100/80/66
100-Pin TQFP 8Mb Pipelined and Flow Through 100 MHz–66 MHz
Commercial Temp
Industrial Temp
Synchronous NBT SRAMs
3.3 V VDD
2.5 V and 3.3 V VDDQ
Features
• 512K x 18 and 256K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Read-Write-Read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• Pin-compatible with 2M, 4M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Pipeline
3-1-1-1
Flow Through
2-1-1-1
-11 -100 -80
-66
tCycle 10 ns 10 ns 12.5 ns 15 ns
tKQ 4.5 ns 4.5 ns 4.8 ns 5 ns
IDD 210 mA 210 mA 190 mA 170 mA
tKQ 11 ns 12 ns 14 ns 18 ns
tCycle 15 ns 15 ns 15 ns 20 ns
IDD 150 mA 150 mA 130 mA 130 mA
Functional Description
The GS881Z18/36T is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS881Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
BC
DE
F
Read/Write
R
WR
WR
W
Flow Through
Data I/O
Pipelined
Data I/O
QA DB QC DD QE
QA DB QC DD QE
Rev: 1.10 8/2000
1/34 © 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.






GS881Z36T Datasheet, Funktion
GS881Z18/36 ByteSafe NBT SRAM Functional Block Diagram
Preliminary.
GS881Z18/36T-11/100/80/66
Rev: 1.10 8/2000
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1998, Giga Semiconductor, Inc.

6 Page









GS881Z36T pdf, datenblatt
Preliminary.
GS881Z18/36T-11/100/80/66
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H or NC
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
ByteSafe Data Parity Control
L or NC
ZZ H
DP
L
H or NC
Active
Standby, IDD = ISB
Check for Odd Parity
Check for Even Parity
Note:
There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Rev: 1.10 8/2000
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1998, Giga Semiconductor, Inc.

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