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GS8673ET18BK Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8673ET18BK
Beschreibung 72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8673ET18BK Datasheet, Funktion
GS8673ET18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaDDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
SigmaDDR-IIIeFamily Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Speed Bin
-675
-625
-550
-500
Parameter Synopsis
Operating Frequency
675 / 450 MHz
625 / 400 MHz
550 / 375 MHz
500 / 333 MHz
Data Rate (per pin)
1350 / 900 Mbps
1250 / 800 Mbps
1100 / 750 Mbps
1000 / 666 Mbps
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
VDD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 5/2012
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS8673ET18BK Datasheet, Funktion
GS8673ET18/36BK-675/625/550/500
Power Up Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The DLL is disabled, regardless of the state of the DLL pin.
• Read and Write operations are ignored.
Note: If possible, RST should be asserted High before input clocks (CK, CK, KD, KD) begin toggling, and remain asserted High
until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing
trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• DQ are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 160K (163,840) cycles.
During this time:
• Output driver and input termination impedances are calibrated (i.e. set to the programmed values).
Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins
immediately after output driver and input termination impedance calibration has completed. If de-asserted Low, DLL
synchronization begins after the DLL pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert DLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles.
During this time:
• The DLL is enabled and synchronized properly.
After DLL synchronization has completed:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Rev: 1.06 5/2012
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS8673ET18BK pdf, datenblatt
GS8673ET18/36BK-675/625/550/500
CK, KD
CK, KD
SA
LD
R/W
DQ
Write1
(Notes 1)
DQ Input Termination Control Timing Diagram (RL = 3 example)
NOPr1
(Note 2)
Read1
(Note 3)
NOPr2
(Note 4)
NOPr3
NOPr4
(Note 5)
NOPw1
(Note 6)
NOPw2
NOPw3
(Note 7)
Write2
(Note 8)
t1 t2 t3
t4 t5
t6
Notes (all timing depicted at the ECCRAM pins):
1. The Controller initiates Write1. It stops driving DQ Low and begins driving valid Write Data ~0.75 cycles later.
Note: At the moment Write1 is initiated, the Controller is driving DQ Low and the ECCRAM is enabling its DQ termination.
2. The Controller initiates one NOPr (NOPr1) before Read1. It completes driving valid Write Data and begins driving DQ Low again ~0.75 cycles later.
In response to NOPr1, the ECCRAM disables its DQ termination and begins driving DQ Low 2 cycles later (in NOPr2), “t1” after the Controller completes
driving valid Write Data and begins driving DQ Low.
Note: t1 = “~1.25 cycles + tKHDQT” above; if it were depicted at the Controller pins, it would increase by 2*tPD, where “tPD” is the trace propagation delay
between Controller and ECCRAM. So, t1 must be >0 at the ECCRAM. As shown, t1 is the minimum it can be, because R/W is driven High in the cycle after
Write1 above. It can be increased by initiating NOPw after Write1, but that is unnecessary to ensure the successful completion of Write1.
Note: This one NOPr before Read1 causes the ECCRAM to drive DQ Low 2 cycles (instead of 1 cycle, without it) before valid Read Data.
3. The Controller initiates Read1. It stops driving DQ Low and enables its DQ termination 2.5 cycles later (in NOPr3), “t2” after the ECCRAM disables its DQ
termination and begins driving DQ Low (in NOPr2), and “t3” before the ECCRAM begins driving valid Read Data (in NOPr4).
In response to Read1, the ECCRAM stops driving DQ Low, and begins driving valid Read Data 3 cycles later (in NOPr4).
Note: t2 = “1.5 cycles - tKHDQT” above; if it were depicted at the Controller pins, t2 would decrease by 2*tPD. So, t2 must be >0 at the Controller.
t2 can be increased by initiating more NOPr in step 2, and decreased by initiating fewer NOPr in step 2.
Note: t3 = “0.5 cycles + tKHDQT” above; if it were depicted at the Controller pins, t3 would increase by 2*tPD. So, t3 must be >0 at the ECCRAM.
As shown, t3 is the minimum it could realistically be. It can be increased if the Controller enables its DQ termination earlier, but then t2 would decrease
accordingly.
4. The Controller initiates two NOPr (NOPr2 ~ NOPr3), to meet the minimum ECCRAM requirement after a Read. It continues to enable its DQ termination.
In response to NOPr3, the ECCRAM completes driving valid Read Data and begins driving DQ Low again 2 cycles later (in NOPw1).
5. The Controller initiates one additional NOPr (NOPr4) before initiating NOPw1. It continues to enable its DQ termination.
Note: This 3rd NOPr before NOPw1 causes the ECCRAM to drive DQ Low 2 cycles (instead of 1 cycle, without it) after valid Read Data.
6. The Controller initiates two NOPw (NOPw1 ~ NOPw2), to meet the minimum ECCRAM requirement before a Write. It disables its DQ termination and
begins driving DQ Low 1.5 cycles later (in NOPw2), “t4” after the ECCRAM stops driving valid Read data and begins driving DQ Low, and “t5” before the
ECCRAM stops driving DQ Low and enables its DQ termination.
In response to NOPw1, the ECCRAM stops driving DQ Low and enables its DQ termination 2 cycles later (in NOPw3).
Note: t4 = “1.5 cycles - tKHDQT” above; if it were depicted at the Controller pins, t4 would decrease by 2*tPD. So, t4 must be >0 at the Controller.
t4 can be increased by initiating more NOPr in step 5, and decreased by initiating fewer NOPr in step 5.
Note: t5 = “0.5 cycles + tKHDQT” above; if it were depicted at the Controller pins, t5 would increase by 2*tPD. So, t5 must be >0 at the ECCRAM.
As shown, t5 is the minimum it could realistically be. It can be increased if the Controller disables its DQ termination earlier, but then t4 would decrease
accordingly.
7. The Controller initiates one additional NOPw (NOPw3) before initiating Write2. It continues to drive DQ Low.
Note: This 3rd NOPw before Write2 causes the ECCRAM to enable its DQ termination “t6” (instead of “t6 - 1 cycle”, without it) before the Controller begins
driving valid Write Data.
8. The Controller initiates Write2. It stops driving DQ Low and begins driving valid Write Data later ~0.75 cycles later, “t6” after the ECCRAM stops driving
DQ Low and enables its termination.
Note: t6 = “~1.75 cycles - tKHDQT” above; if it were depicted at the Controller pins, t6 would decrease by 2*tPD. So, t6 must be >0 at the Controller.
t6 can be increased by initiating more NOPw in step 7, and decreased by initiating fewer NOPw in step 7.
Rev: 1.06 5/2012
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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