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GS881Z36BGT-V Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS881Z36BGT-V
Beschreibung 9Mb Pipelined and Flow Through Synchronous NBT SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS881Z36BGT-V Datasheet, Funktion
GS881Z18/32/36B(T/D)-xxxV
100-Pin TQFP & 165-Bump BGA 9Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
The GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/32/36B(T/D)-xxxV may be configured by the
user to operate in Pipeline or Flow Through mode. Operating
as a pipelined synchronous device, in addition to the rising-
edge-triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's
high performance CMOS technology and is available in
JEDEC-standard 100-pin TQFP and 165-bump BGA packages.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Paramter Synopsis
-250 -200 -150 Unit
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
3.0 3.0 3.8 ns
4.0 5.0 6.7 ns
200 170 140 mA
230 195 160 mA
5.5 6.5 7.5 ns
5.5 6.5 7.5 ns
160 140 128 mA
185 160 145 mA
Rev: 1.00 6/2006
1/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology






GS881Z36BGT-V Datasheet, Funktion
GS881Z18/32/36B(T/D)-xxxV
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 CKE ADV A17 A A
A
B NC A E2 NC BA CK W G NC A NC B
C
NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQA
C
D
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
D
E
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
E
F
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
F
G
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
G
H FT MCH NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
J
K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
K
L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
L
M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
M
N DQB NC VDDQ VSS NC NC NC VSS VDDQ NC NC
N
P
NC NC
A
A TDI A1 TDO A
A
A NC
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.00 6/2006
6/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology

6 Page









GS881Z36BGT-V pdf, datenblatt
GS881Z18/32/36B(T/D)-xxxV
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
R External L-H L L H X L H L L L Q
B Next L-H L H X X X X X L L Q 1,10
R External L-H L L H X L H L H L High-Z 2
B Next L-H L H X X X X X H L High-Z 1,2,10
W External L-H L
L LL L H LXL D
3
B Next L-H L H X L X X X X L D 1,3,10
B Next L-H L H X H X X X X L High-Z 1,2,3,10
D
None L-H L
L X X H X X X L High-Z
D
None L-H L
L X X X X H X L High-Z
D
None L-H L
L X X X L X X L High-Z
D
None L-H L
L L H L H L X L High-Z 1
Deselect Cycle, Continue
D
None L-H L
H X X X X X X L High-Z 1
Sleep Mode
None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall
Current L-H H
X XX X X XXL
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00 6/2006
12/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology

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