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GS8321E36E Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8321E36E
Beschreibung 36Mb Sync Burst SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8321E36E Datasheet, Funktion
GS8321E18/32/36E-250/225/200/166/150/133
165-Bump FP-BGA
Commercial Temp
Industrial Temp
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• Pb-Free 165-bump BGA package available
Functional Description
Applications
The GS8321E18/32/36E is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8321E18/32/36E is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8321E18/32/36E operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
tKQ
tCycle
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3-1-1-1 Curr (x18) 285 250 215 200 190 165 mA
Curr (x32/x36) 330 290 255 235 220 195 mA
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
5.5
5.5
205
235
6.0
6.0
195
225
6.5
6.5
185
210
7.0
7.0
175
200
7.5
7.5
165
190
8.5
8.5
155
175
ns
ns
mA
mA
Rev: 1.03 4/2005
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology






GS8321E36E Datasheet, Funktion
GS8321E18/32/36E-250/225/200/166/150/133
GS8321E18/32/36 Block Diagram
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
E1 D Q
Register
DQ
FT
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
0
A
Memory
Array
Q
36
D
36
44
36
36
36
DQx1DQx9
36
36
4 32
Parity
Encode
4
Parity
Compare
NC NC
Rev: 1.03 4/2005
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

6 Page









GS8321E36E pdf, datenblatt
GS8321E18/32/36E-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
WR
WR
X
First Write
CW
R
CR
W First Read X
CW CR
W
X
R
Burst Write
CR
CW
R
W Burst Read X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 4/2005
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

12 Page





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