Datenblatt-pdf.com


GS8322Z18B Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8322Z18B
Beschreibung 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8322Z18B Datasheet, Funktion
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz 2.5
V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
www.DataSheet42U.5.coVmor 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-Bump BGA package
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
285 265 245 220 210 185 mA
350 320 295 260 240 215 mA
440 410 370 320 300 265 mA
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
205 195 185 175 165 155 mA
235 225 210 200 190 175 mA
315 295 265 255 240 230 mA
Rev: 11/1/04
1/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology






GS8322Z18B Datasheet, Funktion
www.DataSheet4U.com
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
GS8322Z18B Pad Out—119-Bump BGA—Top View (Package B)
1234567
A VDDQ A A A A A VDDQ A
B NC E2 A ADV A E3 NC B
C NC A
A VDD A
A NC C
D DQB NC VSS ZQ VSS DQPA NC
D
E NC DQB VSS E1 VSS NC DQA E
F
VDDQ
NC
VSS
G
VSS
DQA
VDDQ
F
G NC DQB BB A NC NC DQA G
H DQB NC VSS W VSS DQA NC
H
J
VDDQ
VDD
NC
VDD
NC
VDD VDDQ
J
K NC DQB VSS CK VSS NC DQA K
L DQB NC NC NC BA DQA NC
L
M
VDDQ
DQB
VSS
CKE
VSS
NC VDDQ
M
N DQB NC VSS A1 VSS DQA NC
N
P NC DQPB VSS A0 VSS NC DQA P
R NC A LBO VDD FT A NC R
T NC A A A A A ZZ T
U
VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.04 11/2004
6/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology

6 Page









GS8322Z18B pdf, datenblatt
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
www.DataSheet4U.com
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
R External L-H L L H X L H L L L Q
B
Next L-H L
H XX X X XLL Q
1,10
R External L-H L L H X L H L H L High-Z 2
B
Next L-H L
H X X X X X H L High-Z 1,2,10
W External L-H L
L LL L H LXL D
3
B Next L-H L H X L X X X X L D 1,3,10
B
Next L-H L
H X H X X X X L High-Z 1,2,3,10
D
None L-H L
L X X H X X X L High-Z
D
None L-H L
L X X X X H X L High-Z
D
None L-H L
L X X X L X X L High-Z
D
None L-H L
L L H L H L X L High-Z 1
Deselect Cycle, Continue
D
None L-H L
H X X X X X X L High-Z 1
Sleep Mode
None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall
Current L-H H
X XX X X XXL
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.04 11/2004
12/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS8322Z18B Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS8322Z18(GS8322Z18 - GS8322Z72) 36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology
GS8322Z18B36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology
GS8322Z18E36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche