Datenblatt-pdf.com


GS8321Z36GE Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8321Z36GE
Beschreibung 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8321Z36GE Datasheet, Funktion
GS8321Z18/32/36E-250/225/200/166/150/133
165-Bump FP-BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
The GS8321Z18/32/36E is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8321Z18/32/36E may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8321Z18/32/36E is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump FP-BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
tKQ
tCycle
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3-1-1-1 Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
6.5
6.5
205
235
7.0
7.0
195
225
7.5
7.5
185
210
8.0
8.0
175
200
8.5
8.5
165
190
8.5
8.5
155
175
ns
ns
mA
mA
Rev: 1.08 2/2011
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology






GS8321Z36GE Datasheet, Funktion
GS8321Z18/32/36E-250/225/200/166/150/133
GS8321Z18/32/36 NBT SRAM Functional Block Diagram
Rev: 1.08 2/2011
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

6 Page









GS8321Z36GE pdf, datenblatt
GS8321Z18/32/36E-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0]
1st address
00 01 10
2nd address
01 10 11
3rd address
10 11 00
4th address
11 00 01
Note:
The burst counter wraps to initial state on the 5th clock.
A[1:0]
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0]
1st address
00 01 10
2nd address
01 00 11
3rd address
10 11 00
4th address
11 10 01
Note:
The burst counter wraps to initial state on the 5th clock.
A[1:0]
11
10
01
00
Rev: 1.08 2/2011
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS8321Z36GE Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS8321Z36GE36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology
GS8321Z36GE-V36Mb Pipelined and Flow Through Synchronous NBT SRAMGSI Technology
GSI Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche