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GS82582T20GE Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS82582T20GE
Beschreibung 288Mb SigmaDDR-II+ Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 26 Seiten
GS82582T20GE Datasheet, Funktion
GS82582T20/38GE-550/500/450/400
165-Bump BGA
Commercial Temp
Industrial Temp
288Mb SigmaDDR-II+TM
Burst of 2 SRAM
550 MHz–400 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDRTM Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
SigmaDDR-IIFamily Overview
The GS82582T20/38GE are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582T20/38GE SigmaDDR-II+ SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582T20/38GE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-550
1.81 ns
0.45 ns
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
Rev: 1.04 4/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology






GS82582T20GE Datasheet, Funktion
GS82582T20/38GE-550/500/450/400
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1
Beat 1
01
Beat 2
10
D0–D8
Data In
Don’t Care
D9–D17
Don’t Care
Data In
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaDDR-II+ SRAMs are supplied with programmable input termination on Data (DQ), Byte Write (BW), and Clock (K,
K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating–the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is
enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175and 250. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Notes:
1. When ODT = 1, Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, BW, K, K inputs
should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the
input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the
receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result
in the device’s operating currents being higher.
2. When ODT = 1, DQ input termination is enabled during Write and NOP operations, and disabled during Read operations.
Specifically, DQ input termination is disabled 0.5 cycles before the SRAM enables its DQ drivers and starts driving valid Read
Data, and remains disabled until 0.5 cycles after the SRAM stops driving valid Read Data and disables its DQ drivers; DQ
input termination is enabled at all other times. Consequently, the SRAM Controller should disable its DQ input termination,
enable its DQ drivers, and drive DQ inputs (High or Low) during Write and NOP operations. And, it should enable its DQ
input termination and disable its DQ drivers during Read operations. Care should be taken during Write or NOP -> Read
transitions, and during Read -> NOP transitions, to minimize the time during which one device (SRAM or SRAM Controller)
has enabled its DQ input termination while the other device has not yet enabled its DQ driver. Otherwise, the input termination
will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-
stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating
currents being higher.
Rev: 1.04 4/2016
6/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

6 Page









GS82582T20GE pdf, datenblatt
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
CIN
COUT
CCLK
GS82582T20/38GE-550/500/450/400
Test conditions
VIN = 0 V
VOUT = 0 V
VIN = 0 V
Typ. Max. Unit
4 5 pF
6 7 pF
5 6 pF
AC Test Conditions
Parameter
Input high level
Input low level
Max. input slew rate
Input reference level
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
1.25 V
0.25 V
2 V/ns
0.75 V
VDDQ/2
AC Test Load Diagram
DQ
RQ = 250 (HSTL I/O)
50VREF = 0.75 V
VT = VDDQ/2
Input and Output Leakage Characteristics
Parameter
Input Leakage Current
(except mode pins)
Doff
ODT
Symbol
IIL
IILDOFF
IILODT
Output Leakage Current
IOL
Test Conditions
VIN = 0 to VDD
VIN = 0 to VDD
VIN = 0 to VDD
Output Disable,
VOUT = 0 to VDDQ
Min.
–2 uA
–20 uA
–2 uA
–2 uA
Max
2 uA
2 uA
20 uA
2 uA
Rev: 1.04 4/2016
12/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

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