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GS82582S18GE Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS82582S18GE
Beschreibung 288Mb SigmaSIO DDR-II Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS82582S18GE Datasheet, Funktion
GS82582S18/36GE-400/375/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
288Mb SigmaSIOTM DDR-II
Burst of 2 SRAM
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
SigmaSIOFamily Overview
GS82582S18/36GE are built in compliance with the SigmaSIO
DDR-II SRAM pinout standard for Separate I/O synchronous
SRAMs. They are 301,989,888-bit (288Mb) SRAMs. These
are the first in a family of wide, very low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Clocking and Addressing Schemes
A Burst of 2SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead. Each Burst of 2SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-375
2.66 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.04 4/2016
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology






GS82582S18GE Datasheet, Funktion
GS82582S18/36GE-400/375/333/300/250
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1
Beat 1
01
Beat 2
10
D0–D8
Data In
Don’t Care
D9–D17
Don’t Care
Data In
Resulting Write Operation
D0–D8
Written
Beat 1
D9–D17
Unchanged
D0–D8
Unchanged
Beat 2
D9–D17
Written
Output Register Control
SigmaSIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the
Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing
of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of
the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
Rev: 1.04 4/2016
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

6 Page









GS82582S18GE pdf, datenblatt
GS82582S18/36GE-400/375/333/300/250
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O Voltage on I/O Pins
–0.5 to VDDQ +0.3 (2.9 V max.)
V
VIN Voltage on Other Input Pins
–0.5 to VDDQ +0.3 (2.9 V max.)
V
IIN Input Current on Any Pin
+/–100
mA dc
IOUT Output Current on Any I/O Pin
+/–100
mA dc
TJ Maximum Junction Temperature
125 oC
TSTG Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min. Typ. Max. Unit
Supply Voltage
VDD 1.7 1.8 1.9 V
I/O Supply Voltage
VDDQ
1.4 — VDD V
Reference Voltage
VREF 0.68 — 0.95 V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions)
TJ
0 25 85 C
Junction Temperature
(Industrial Range Versions)*
TJ
–40 25 100 C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.04 4/2016
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

12 Page





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