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GS8182T37BGD Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8182T37BGD
Beschreibung 18Mb SigmaDDR-II+ Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 27 Seiten
GS8182T37BGD Datasheet, Funktion
GS8182T19/37BD-435/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb SigmaDDR-II+TM
Burst of 2 SRAM
435 MHz–300 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-IIFamily Overview
The GS8182T19/37BD are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182T19/37BD SigmaDDR-II SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182T19/37BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 2M x 8 has a 1M
addressable index).
tKHKH
tKHQV
-435
2.3 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.03a 11/2011
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology






GS8182T37BGD Datasheet, Funktion
GS8182T19/37BD-435/400/375/333/300
Power-Up Sequence for SigmaQuad-II+ SRAMs
For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs be powered-up in a specific sequence in order to avoid unde-
fined operations
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to high.
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30ns. 2048 cycles of clean K clocks are
always required to re-lock the DLL after reset.
DLL Constraints
The DLL synchronizes to either K clock. These clocks should have low phase jitter (tKCVar).
• The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock
frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or
failures during the initial stage.
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1
Beat 1
01
Beat 2
10
D0–D8
Data In
Don’t Care
D9–D17
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Written
Beat 1
Byte 2
D9–D17
Unchanged
Byte 3
D0–D8
Unchanged
Beat 2
Byte 4
D9–D17
Written
Rev: 1.03a 11/2011
6/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology

6 Page









GS8182T37BGD pdf, datenblatt
GS8182T19/37BD-435/400/375/333/300
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Output High Voltage
VOH1
VDDQ/2
Output Low Voltage
VOL1
Vss
Output High Voltage
VOH2
VDDQ – 0.2
Output Low Voltage
VOL2
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Vss
Max.
VDDQ
VDDQ/2
VDDQ
0.2
Units
V
V
V
V
Notes
1, 3
2, 3
4, 5
4, 6
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.03a 11/2011
12/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology

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