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GS8182T18BGD Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8182T18BGD
Beschreibung 18Mb SigmaDDR-II Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8182T18BGD Datasheet, Funktion
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb SigmaDDR-II™
Burst of 2 SRAM
400 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-IIFamily Overview
The GS8182T08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182T08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182T08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 is used to initialize the pointers that control the data
multiplexer / de-multiplexer so the RAM can perform "critical
word first" operations. From an external address point of view,
regardless of the starting point, the data transfers always follow
the same sequence {0, 1} or {1, 0} (where the digits shown
represent A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B2 RAMs are one address pin less than the advertised index
depth (e.g., the 2M x 8 has a 1M addressable index, and A0 is
not an accessible address pin).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.04c 11/2011
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology






GS8182T18BGD Datasheet, Funktion
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Read/Write Control Pin
Input Write Active Low; Read Active High
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
NW0–NW1
Nybble Write Control Pin
Input
Active Low
x8 only
BW
Byte Write Control Pin
Input
Active Low
x9 only
LD
Synchronous Load Pin
Input Active Low
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
C
Output Clock
Input Active High
C
Output Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.5 V or 1.8 V Nominal
VSS
Power Supply: Ground
Supply
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to VREF voltage.
Rev: 1.04c 11/2011
6/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

6 Page









GS8182T18BGD pdf, datenblatt
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
B2 Nybble Write Clock Truth Table
NW NW
Current Operation
K
(tn+1)
T
T
K
(tn+2)
T
F
K
(tn)
Write
Dx stored if NWn = 0 in both data transfers
Write
Dx stored if NWn = 0 in 1st data transfer only
FT
Write
Dx stored if NWn = 0 in 2nd data transfer only
FF
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K
(tn+1)
D1
D1
X
X
D
K
(tn+2)
D2
X
D2
X
x36 Byte Write Enable (BWn) Truth Table
BW0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BW1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
BW2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BW3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Rev: 1.04c 11/2011
12/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

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