GS8182Q18D Datasheet PDF - GSI Technology
| Part Number | GS8182Q18D | |
| Description | 18Mb Burst of 2 SigmaQuad-II SRAM | |
| Manufacturers | GSI Technology | |
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Preliminary
GS8182Q18D-200/167/133
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaQuad-II SRAM
200MHz–133MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
SigmaRAM™ Family Overview
GS8182Q18 are built in compliance with the SigmaQuad-II
SRAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage HSTL I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaQuad-II SRAM is a synchronous device. It
employs two input register clock inputs, K and K. K and K are
independent single-ended clock inputs, not differential inputs
to a single differential clock input buffer. The device also
allows the user to manipulate the output register clock inputs
quasi independently with the C and C clock inputs. C and C are
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
also independent single-ended clock inputs, not differential
inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
tKHKH
tKHQV
Parameter Synopsis
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
-133
7.5 ns
0.5 ns
Rev: 1.02 11/2004
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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Preliminary
GS8182Q18D-200/167/133
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied
high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the
Read Enable-bar pin, R, begins a read port deselect cycle.
Burst of 2 Double Data Rate SigmaQuad-II SRAM Read First
Read A
NOP
Write B
Read C Write D Read E Write F Read G Write H NOP
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
A
BC
DE
FG
H
B B+1 D D+1 F F+1 H H+1
A A+1
C C+1 E E+1 G
Rev: 1.02 11/2004
5/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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| Information | Total 28 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ GS8182Q18D.PDF Datasheet ] | |
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