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GS8182S36BGD Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8182S36BGD
Beschreibung 18Mb Burst of 2 SigmaSIO DDR-II SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS8182S36BGD Datasheet, Funktion
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaSIO DDR-IITM SRAM
400 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaSIO DDR-IIFamily Overview
GS8182S08/09/18/36BD are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 2M x 8 has a 1M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.03c 11/2011
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology






GS8182S36BGD Datasheet, Funktion
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Read/Write Contol Pin
Input Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Only
BW
Synchronous Byte Writes
Input
Active Low
x09 Only
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 Only
K
Input Clock
Input Active High
C
Output Clock
Input Active High
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
K
Input Clock
Input Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
— Active Low
LD
Synchronous Load Pin
— Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input —
Qn
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
NC
No Connect
——
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin.
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
Rev: 1.03c 11/2011
6/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

6 Page









GS8182S36BGD pdf, datenblatt
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A LD R/W
Current
Operation
DDQQ
KKK
(tn) (tn) (tn)
K
(tn)
K
(tn+1)
K
(tn+1)
K
(tn+1)
K
(tn+1)
X1X
Deselect
X — Hi-Z —
V01
Read
X — Q0 Q1
V00
Write
D0 D1 Hi-Z —
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
x18 Byte Write Clock Truth Table
BW BW
Current Operation
K
(tn+1)
K
(tn+2)
K
(tn)
TT
Write
Dx stored if BWn = 0 in both data transfers
TF
Write
Dx stored if BWn = 0 in 1st data transfer only
FT
Write
Dx stored if BWn = 0 in 2nd data transfer only
FF
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.03c 11/2011
12/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
K
(tn+1)
D1
D1
X
X
D
K
(tn+2)
D2
X
D2
X
© 2007, GSI Technology

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