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GS4288C09L Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS4288C09L
Beschreibung 288Mb CIO Low Latency DRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS4288C09L Datasheet, Funktion
GS4288C09/18/36L
144-Ball BGA
Commercial Temp
Industrial Temp
32M x 9, 16M x 18, 8M x 36
288Mb CIO Low Latency DRAM (LLDRAM) II
533 MHz300 MHz
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 8M x 36, 16M x 18, and 32M x 9 organizations available
• 8 internal banks for concurrent operation and maximum
bandwidth
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60matched impedance outputs
• 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O
• On-die termination (ODT) RTT
• Commerical and Industrial Temperature
Commercial (+0° TC +95°C)
Industrial (–40° TC +95°C)
Introduction
The GSI Technology 288Mb Low Latency DRAM
(LLDRAM) II is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V VEXT and 1.8 V VDD for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent BGA 144-ball package.
Rev: 1.03 7/2014
1/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS4288C09L Datasheet, Funktion
GS4288C09/18/36L
Ball Descriptions (Continued)
Symbol
QVLD
Type
Output
Description
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
TDO
Output
IEEE 1149.1 Test Output—JTAG output. This ball may be left as no connect if the JTAG function is not
used.
VDD
Supply
Power Supply—Nominally, 1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VDDQ
Supply
DQ Power Supply—Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
VEXT
Supply
Power Supply—Nominally, 2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VSS Supply Ground
VTT
Power Supply—Isolated termination supply. Nominally, VDDQ/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
A21, A22
Reserved for Future Use—This signal is not connected and may be connected to ground.
DNU — Do Not Use—These balls may be connected to ground.
NF — No Function—These balls can be connected to ground.
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) . Start clock after the supply voltages are stable. Apply VDD and VEXT before or
at the same time as VDDQ1. Apply VDDQ before or at the same time as VREF and VTT. The chip starts internal initlization
only after both voltages approach their nominal levels. CK/CK must meet VID(DC) prior to being applied2. Apply only
NOP commands to start. Ensuring CK/CK meet VID(DC) while loading NOP commands guarantees that the LLDRAM II
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II. tMRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
Rev: 1.03 7/2014
6/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS4288C09L pdf, datenblatt
T0
CK
CK
CMD RD
ADDR
A
BA BA0
QKx
QKx
QVLD
DQ
ODT
GS4288C09/18/36L
Read NOP Read On-Die Termination Burst Length 2, Configuration 1
T1 T2 T3 T4 T5 T6 T7
T8
NOP RD NOP NOP NOP NOP NOP NOP
A
BA2
RL = 4
ODT ON
Q0a Q0b
ODT OFF
ODT ON
Q2a Q2b
ODT OFF
ODT ON
T0
CK
CK
CMD RD
ADDR
A
BA BA0
DK
DK
DQ
QKx
QKx
QVLD
ODT
Read-Write On-Die Termination Burst Length 2, Configuration 1
T1 T2 T3 T4 T5 T6 T7
WT NOP NOP NOP NOP NOP NOP
A
BA1
WL = 5
RL = 4
Q0a Q0b
D1a D1b
ODT ON
ODT OFF
ODT ON
T8
NOP
Rev: 1.03 7/2014
12/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

12 Page





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